1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19	model = "Turris Omnia";
20	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22	chosen {
23		stdout-path = &uart0;
24	};
25
26	aliases {
27		ethernet0 = &eth0;
28		ethernet1 = &eth1;
29		ethernet2 = &eth2;
30	};
31
32	memory {
33		device_type = "memory";
34		reg = <0x00000000 0x40000000>; /* 1024 MB */
35	};
36
37	soc {
38		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
39			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
40			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
41			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
42			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
43
44		internal-regs {
45
46			/* USB part of the PCIe2/USB 2.0 port */
47			usb@58000 {
48				status = "okay";
49			};
50
51			sata@a8000 {
52				status = "okay";
53			};
54
55			sdhci@d8000 {
56				pinctrl-names = "default";
57				pinctrl-0 = <&sdhci_pins>;
58				status = "okay";
59
60				bus-width = <8>;
61				no-1-8-v;
62				non-removable;
63			};
64
65			usb3@f0000 {
66				status = "okay";
67			};
68
69			usb3@f8000 {
70				status = "okay";
71			};
72		};
73
74		pcie {
75			status = "okay";
76
77			pcie@1,0 {
78				/* Port 0, Lane 0 */
79				status = "okay";
80				slot-power-limit-milliwatt = <10000>;
81			};
82
83			pcie@2,0 {
84				/* Port 1, Lane 0 */
85				status = "okay";
86				slot-power-limit-milliwatt = <10000>;
87			};
88
89			pcie@3,0 {
90				/* Port 2, Lane 0 */
91				status = "okay";
92				slot-power-limit-milliwatt = <10000>;
93			};
94		};
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp";
99		i2c-bus = <&sfp_i2c>;
100		tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
101		tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
102		rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
103		los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
104		mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
105		maximum-power-milliwatt = <3000>;
106
107		/*
108		 * For now this has to be enabled at boot time by U-Boot when
109		 * a SFP module is present. Read more in the comment in the
110		 * eth2 node below.
111		 */
112		status = "disabled";
113	};
114};
115
116&bm {
117	status = "okay";
118};
119
120&bm_bppi {
121	status = "okay";
122};
123
124/* Connected to 88E6176 switch, port 6 */
125&eth0 {
126	pinctrl-names = "default";
127	pinctrl-0 = <&ge0_rgmii_pins>;
128	status = "okay";
129	phy-mode = "rgmii";
130	buffer-manager = <&bm>;
131	bm,pool-long = <0>;
132	bm,pool-short = <3>;
133
134	fixed-link {
135		speed = <1000>;
136		full-duplex;
137	};
138};
139
140/* Connected to 88E6176 switch, port 5 */
141&eth1 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&ge1_rgmii_pins>;
144	status = "okay";
145	phy-mode = "rgmii";
146	buffer-manager = <&bm>;
147	bm,pool-long = <1>;
148	bm,pool-short = <3>;
149
150	fixed-link {
151		speed = <1000>;
152		full-duplex;
153	};
154};
155
156/* WAN port */
157&eth2 {
158	/*
159	 * eth2 is connected via a multiplexor to both the SFP cage and to
160	 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
161	 * a SFP module is present, as determined by the mode-def0 GPIO.
162	 *
163	 * Until kernel supports this configuration properly, in case SFP module
164	 * is present, U-Boot has to enable the sfp node above, remove phy
165	 * handle and add managed = "in-band-status" property.
166	 */
167	status = "okay";
168	phy-mode = "sgmii";
169	phy-handle = <&phy1>;
170	phys = <&comphy5 2>;
171	sfp = <&sfp>;
172	buffer-manager = <&bm>;
173	bm,pool-long = <2>;
174	bm,pool-short = <3>;
175};
176
177&i2c0 {
178	pinctrl-names = "default";
179	pinctrl-0 = <&i2c0_pins>;
180	status = "okay";
181
182	i2cmux@70 {
183		compatible = "nxp,pca9547";
184		#address-cells = <1>;
185		#size-cells = <0>;
186		reg = <0x70>;
187
188		i2c@0 {
189			#address-cells = <1>;
190			#size-cells = <0>;
191			reg = <0>;
192
193			/* MCU command i2c API */
194			mcu: mcu@2a {
195				compatible = "cznic,turris-omnia-mcu";
196				reg = <0x2a>;
197				gpio-controller;
198				#gpio-cells = <3>;
199			};
200
201			led-controller@2b {
202				compatible = "cznic,turris-omnia-leds";
203				reg = <0x2b>;
204				#address-cells = <1>;
205				#size-cells = <0>;
206				status = "okay";
207
208				/*
209				 * LEDs are controlled by MCU (STM32F0) at
210				 * address 0x2b.
211				 *
212				 * LED functions are not stable yet:
213				 * - there are 3 LEDs connected via MCU to PCIe
214				 *   ports. One of these ports supports mSATA.
215				 *   There is no mSATA nor PCIe function.
216				 *   For now we use LED_FUNCTION_WLAN, since
217				 *   in most cases users have wifi cards in
218				 *   these slots
219				 * - there are 2 LEDs dedicated for user: A and
220				 *   B. Again there is no such function defined.
221				 *   For now we use LED_FUNCTION_INDICATOR
222				 */
223
224				multi-led@0 {
225					reg = <0x0>;
226					color = <LED_COLOR_ID_RGB>;
227					function = LED_FUNCTION_INDICATOR;
228					function-enumerator = <2>;
229				};
230
231				multi-led@1 {
232					reg = <0x1>;
233					color = <LED_COLOR_ID_RGB>;
234					function = LED_FUNCTION_INDICATOR;
235					function-enumerator = <1>;
236				};
237
238				multi-led@2 {
239					reg = <0x2>;
240					color = <LED_COLOR_ID_RGB>;
241					function = LED_FUNCTION_WLAN;
242					function-enumerator = <3>;
243				};
244
245				multi-led@3 {
246					reg = <0x3>;
247					color = <LED_COLOR_ID_RGB>;
248					function = LED_FUNCTION_WLAN;
249					function-enumerator = <2>;
250				};
251
252				multi-led@4 {
253					reg = <0x4>;
254					color = <LED_COLOR_ID_RGB>;
255					function = LED_FUNCTION_WLAN;
256					function-enumerator = <1>;
257				};
258
259				multi-led@5 {
260					reg = <0x5>;
261					color = <LED_COLOR_ID_RGB>;
262					function = LED_FUNCTION_WAN;
263				};
264
265				multi-led@6 {
266					reg = <0x6>;
267					color = <LED_COLOR_ID_RGB>;
268					function = LED_FUNCTION_LAN;
269					function-enumerator = <4>;
270				};
271
272				multi-led@7 {
273					reg = <0x7>;
274					color = <LED_COLOR_ID_RGB>;
275					function = LED_FUNCTION_LAN;
276					function-enumerator = <3>;
277				};
278
279				multi-led@8 {
280					reg = <0x8>;
281					color = <LED_COLOR_ID_RGB>;
282					function = LED_FUNCTION_LAN;
283					function-enumerator = <2>;
284				};
285
286				multi-led@9 {
287					reg = <0x9>;
288					color = <LED_COLOR_ID_RGB>;
289					function = LED_FUNCTION_LAN;
290					function-enumerator = <1>;
291				};
292
293				multi-led@a {
294					reg = <0xa>;
295					color = <LED_COLOR_ID_RGB>;
296					function = LED_FUNCTION_LAN;
297					function-enumerator = <0>;
298				};
299
300				multi-led@b {
301					reg = <0xb>;
302					color = <LED_COLOR_ID_RGB>;
303					function = LED_FUNCTION_POWER;
304				};
305			};
306
307			eeprom@54 {
308				compatible = "atmel,24c64";
309				reg = <0x54>;
310
311				/* The EEPROM contains data for bootloader.
312				 * Contents:
313				 * 	struct omnia_eeprom {
314				 * 		u32 magic; (=0x0341a034 in LE)
315				 *		u32 ramsize; (in GiB)
316				 * 		char regdomain[4];
317				 * 		u32 crc32;
318				 * 	};
319				 */
320			};
321		};
322
323		i2c@1 {
324			#address-cells = <1>;
325			#size-cells = <0>;
326			reg = <1>;
327
328			/* routed to PCIe0/mSATA connector (CN7A) */
329		};
330
331		i2c@2 {
332			#address-cells = <1>;
333			#size-cells = <0>;
334			reg = <2>;
335
336			/* routed to PCIe1/USB2 connector (CN61A) */
337		};
338
339		i2c@3 {
340			#address-cells = <1>;
341			#size-cells = <0>;
342			reg = <3>;
343
344			/* routed to PCIe2 connector (CN62A) */
345		};
346
347		sfp_i2c: i2c@4 {
348			#address-cells = <1>;
349			#size-cells = <0>;
350			reg = <4>;
351
352			/* routed to SFP+ */
353		};
354
355		i2c@5 {
356			#address-cells = <1>;
357			#size-cells = <0>;
358			reg = <5>;
359
360			/* ATSHA204A-MAHDA-T crypto module */
361			crypto@64 {
362				compatible = "atmel,atsha204a";
363				reg = <0x64>;
364			};
365		};
366
367		i2c@6 {
368			#address-cells = <1>;
369			#size-cells = <0>;
370			reg = <6>;
371
372			/* exposed on pin header */
373		};
374
375		i2c@7 {
376			#address-cells = <1>;
377			#size-cells = <0>;
378			reg = <7>;
379
380			pcawan: gpio@71 {
381				/*
382				 * GPIO expander for SFP+ signals and
383				 * and phy irq
384				 */
385				compatible = "nxp,pca9538";
386				reg = <0x71>;
387
388				pinctrl-names = "default";
389				pinctrl-0 = <&pcawan_pins>;
390
391				interrupt-parent = <&gpio1>;
392				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
393
394				gpio-controller;
395				#gpio-cells = <2>;
396			};
397		};
398	};
399};
400
401&mdio {
402	pinctrl-names = "default";
403	pinctrl-0 = <&mdio_pins>;
404	status = "okay";
405
406	phy1: ethernet-phy@1 {
407		compatible = "ethernet-phy-ieee802.3-c22";
408		reg = <1>;
409		marvell,reg-init = <3 18 0 0x4985>,
410				   <3 16 0xfff0 0x0001>;
411
412		/* irq is connected to &pcawan pin 7 */
413	};
414
415	/* Switch MV88E6176 at address 0x10 */
416	switch@10 {
417		pinctrl-names = "default";
418		pinctrl-0 = <&swint_pins>;
419		compatible = "marvell,mv88e6085";
420		#address-cells = <1>;
421		#size-cells = <0>;
422
423		dsa,member = <0 0>;
424		reg = <0x10>;
425
426		interrupt-parent = <&gpio1>;
427		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
428
429		ports {
430			#address-cells = <1>;
431			#size-cells = <0>;
432
433			ports@0 {
434				reg = <0>;
435				label = "lan0";
436			};
437
438			ports@1 {
439				reg = <1>;
440				label = "lan1";
441			};
442
443			ports@2 {
444				reg = <2>;
445				label = "lan2";
446			};
447
448			ports@3 {
449				reg = <3>;
450				label = "lan3";
451			};
452
453			ports@4 {
454				reg = <4>;
455				label = "lan4";
456			};
457
458			ports@5 {
459				reg = <5>;
460				label = "cpu";
461				ethernet = <&eth1>;
462				phy-mode = "rgmii-id";
463
464				fixed-link {
465					speed = <1000>;
466					full-duplex;
467				};
468			};
469
470			/* port 6 is connected to eth0 */
471		};
472	};
473};
474
475&pinctrl {
476	pcawan_pins: pcawan-pins {
477		marvell,pins = "mpp46";
478		marvell,function = "gpio";
479	};
480
481	swint_pins: swint-pins {
482		marvell,pins = "mpp45";
483		marvell,function = "gpio";
484	};
485
486	spi0cs0_pins: spi0cs0-pins {
487		marvell,pins = "mpp25";
488		marvell,function = "spi0";
489	};
490
491	spi0cs2_pins: spi0cs2-pins {
492		marvell,pins = "mpp26";
493		marvell,function = "spi0";
494	};
495};
496
497&spi0 {
498	pinctrl-names = "default";
499	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
500	status = "okay";
501
502	flash@0 {
503		compatible = "spansion,s25fl164k", "jedec,spi-nor";
504		#address-cells = <1>;
505		#size-cells = <1>;
506		reg = <0>;
507		spi-max-frequency = <40000000>;
508
509		partitions {
510			compatible = "fixed-partitions";
511			#address-cells = <1>;
512			#size-cells = <1>;
513
514			partition@0 {
515				reg = <0x0 0x00100000>;
516				label = "U-Boot";
517			};
518
519			partition@100000 {
520				reg = <0x00100000 0x00700000>;
521				label = "Rescue system";
522			};
523		};
524	};
525
526	/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
527};
528
529&uart0 {
530	/* Pin header CN10 */
531	pinctrl-names = "default";
532	pinctrl-0 = <&uart0_pins>;
533	status = "okay";
534};
535
536&uart1 {
537	/* Pin header CN11 */
538	pinctrl-names = "default";
539	pinctrl-0 = <&uart1_pins>;
540	status = "okay";
541};
542