1/*
2 * This device tree is copied from
3 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
4 */
5#include "skeleton.dtsi"
6
7/ {
8	model = "Aspeed BMC";
9	compatible = "aspeed,ast2500";
10	#address-cells = <1>;
11	#size-cells = <1>;
12	interrupt-parent = <&vic>;
13
14	aliases {
15		i2c0 = &i2c0;
16		i2c1 = &i2c1;
17		i2c2 = &i2c2;
18		i2c3 = &i2c3;
19		i2c4 = &i2c4;
20		i2c5 = &i2c5;
21		i2c6 = &i2c6;
22		i2c7 = &i2c7;
23		i2c8 = &i2c8;
24		i2c9 = &i2c9;
25		i2c10 = &i2c10;
26		i2c11 = &i2c11;
27		i2c12 = &i2c12;
28		i2c13 = &i2c13;
29		serial0 = &uart1;
30		serial1 = &uart2;
31		serial2 = &uart3;
32		serial3 = &uart4;
33		serial4 = &uart5;
34		serial5 = &vuart;
35	};
36
37	cpus {
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		cpu@0 {
42			compatible = "arm,arm1176jzf-s";
43			device_type = "cpu";
44			reg = <0>;
45		};
46	};
47
48	memory@80000000 {
49		device_type = "memory";
50		reg = <0x80000000 0>;
51	};
52
53	ahb {
54		compatible = "simple-bus";
55		#address-cells = <1>;
56		#size-cells = <1>;
57		ranges;
58
59		fmc: flash-controller@1e620000 {
60			reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
61			#address-cells = <1>;
62			#size-cells = <0>;
63			compatible = "aspeed,ast2500-fmc";
64			clocks = <&scu ASPEED_CLK_AHB>;
65			num-cs = <3>;
66			status = "disabled";
67
68			flash@0 {
69				reg = < 0 >;
70				compatible = "jedec,spi-nor";
71				status = "disabled";
72			};
73
74			flash@1 {
75				reg = < 1 >;
76				compatible = "jedec,spi-nor";
77				status = "disabled";
78			};
79
80			flash@2 {
81				reg = < 2 >;
82				compatible = "jedec,spi-nor";
83				status = "disabled";
84			};
85		};
86
87		spi1: flash-controller@1e630000 {
88			reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
89			#address-cells = <1>;
90			#size-cells = <0>;
91			compatible = "aspeed,ast2500-spi";
92			clocks = <&scu ASPEED_CLK_AHB>;
93			num-cs = <2>;
94			status = "disabled";
95
96			flash@0 {
97				reg = < 0 >;
98				compatible = "jedec,spi-nor";
99				status = "disabled";
100			};
101
102			flash@1 {
103				reg = < 1 >;
104				compatible = "jedec,spi-nor";
105				status = "disabled";
106			};
107		};
108
109		spi2: flash-controller@1e631000 {
110			reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
111			#address-cells = <1>;
112			#size-cells = <0>;
113			compatible = "aspeed,ast2500-spi";
114			clocks = <&scu ASPEED_CLK_AHB>;
115			num-cs = <2>;
116			status = "disabled";
117
118			flash@0 {
119				reg = < 0 >;
120				compatible = "jedec,spi-nor";
121				status = "disabled";
122			};
123
124			flash@1 {
125				reg = < 1 >;
126				compatible = "jedec,spi-nor";
127				status = "disabled";
128			};
129		};
130
131		vic: interrupt-controller@1e6c0080 {
132			compatible = "aspeed,ast2400-vic";
133			interrupt-controller;
134			#interrupt-cells = <1>;
135			valid-sources = <0xfefff7ff 0x0807ffff>;
136			reg = <0x1e6c0080 0x80>;
137		};
138
139		mac0: ethernet@1e660000 {
140			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
141			reg = <0x1e660000 0x180>;
142			interrupts = <2>;
143			status = "disabled";
144		};
145
146		mac1: ethernet@1e680000 {
147			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
148			reg = <0x1e680000 0x180>;
149			interrupts = <3>;
150			status = "disabled";
151		};
152
153		ehci0: usb@1e6a1000 {
154			compatible = "aspeed,ast2500-ehci", "generic-ehci";
155			reg = <0x1e6a1000 0x100>;
156			interrupts = <5>;
157			status = "disabled";
158		};
159
160		ehci1: usb@1e6a3000 {
161			compatible = "aspeed,ast2500-ehci", "generic-ehci";
162			reg = <0x1e6a3000 0x100>;
163			interrupts = <13>;
164			status = "disabled";
165		};
166
167		uhci: usb@1e6b0000 {
168			compatible = "aspeed,ast2500-uhci", "generic-uhci";
169			reg = <0x1e6b0000 0x100>;
170			interrupts = <14>;
171			#ports = <2>;
172			status = "disabled";
173		};
174
175		apb {
176			compatible = "simple-bus";
177			#address-cells = <1>;
178			#size-cells = <1>;
179			ranges;
180
181			syscon: syscon@1e6e2000 {
182				compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
183				reg = <0x1e6e2000 0x1a8>;
184				#clock-cells = <1>;
185				#reset-cells = <1>;
186
187				pinctrl: pinctrl {
188					compatible = "aspeed,g5-pinctrl";
189					aspeed,external-nodes = <&gfx &lhc>;
190
191				};
192			};
193
194			rng: hwrng@1e6e2078 {
195				compatible = "timeriomem_rng";
196				reg = <0x1e6e2078 0x4>;
197				period = <1>;
198				quality = <100>;
199			};
200
201			gfx: display@1e6e6000 {
202				compatible = "aspeed,ast2500-gfx", "syscon";
203				reg = <0x1e6e6000 0x1000>;
204				reg-io-width = <4>;
205			};
206
207			adc: adc@1e6e9000 {
208				compatible = "aspeed,ast2500-adc";
209				reg = <0x1e6e9000 0xb0>;
210				#io-channel-cells = <1>;
211				status = "disabled";
212			};
213
214			sram@1e720000 {
215				compatible = "mmio-sram";
216				reg = <0x1e720000 0x9000>;	// 36K
217			};
218
219			sdmmc: sd-controller@1e740000 {
220				compatible = "aspeed,ast2500-sd-controller";
221				reg = <0x1e740000 0x100>;
222				#address-cells = <1>;
223				#size-cells = <1>;
224				ranges = <0 0x1e740000 0x10000>;
225				clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
226				status = "disabled";
227
228				sdhci0: sdhci@100 {
229					compatible = "aspeed,ast2500-sdhci";
230					reg = <0x100 0x100>;
231					interrupts = <26>;
232					sdhci,auto-cmd12;
233					clocks = <&scu ASPEED_CLK_SDIO>;
234					status = "disabled";
235				};
236
237				sdhci1: sdhci@200 {
238					compatible = "aspeed,ast2500-sdhci";
239					reg = <0x200 0x100>;
240					interrupts = <26>;
241					sdhci,auto-cmd12;
242					clocks = <&scu ASPEED_CLK_SDIO>;
243					status = "disabled";
244				};
245			};
246
247			gpio: gpio@1e780000 {
248				#gpio-cells = <2>;
249				gpio-controller;
250				compatible = "aspeed,ast2500-gpio";
251				reg = <0x1e780000 0x1000>;
252				interrupts = <20>;
253				gpio-ranges = <&pinctrl 0 0 220>;
254				ngpios = <228>;
255				interrupt-controller;
256			};
257
258			timer: timer@1e782000 {
259				/* This timer is a Faraday FTTMR010 derivative */
260				compatible = "aspeed,ast2400-timer";
261				reg = <0x1e782000 0x90>;
262			};
263
264			uart1: serial@1e783000 {
265				compatible = "ns16550a";
266				reg = <0x1e783000 0x20>;
267				reg-shift = <2>;
268				interrupts = <9>;
269				no-loopback-test;
270				status = "disabled";
271			};
272
273			uart5: serial@1e784000 {
274				compatible = "ns16550a";
275				reg = <0x1e784000 0x20>;
276				reg-shift = <2>;
277				interrupts = <10>;
278				no-loopback-test;
279				status = "disabled";
280			};
281
282			wdt1: watchdog@1e785000 {
283				compatible = "aspeed,wdt";
284				reg = <0x1e785000 0x1c>;
285				interrupts = <27>;
286			};
287
288			wdt2: watchdog@1e785020 {
289				compatible = "aspeed,wdt";
290				reg = <0x1e785020 0x1c>;
291				interrupts = <27>;
292				status = "disabled";
293			};
294
295			wdt3: watchdog@1e785040 {
296				compatible = "aspeed,wdt";
297				reg = <0x1e785040 0x1c>;
298				status = "disabled";
299			};
300
301			pwm_tacho: pwm-tacho-controller@1e786000 {
302				compatible = "aspeed,ast2500-pwm-tacho";
303				#address-cells = <1>;
304				#size-cells = <0>;
305				reg = <0x1e786000 0x1000>;
306				status = "disabled";
307			};
308
309			vuart: serial@1e787000 {
310				compatible = "aspeed,ast2500-vuart";
311				reg = <0x1e787000 0x40>;
312				reg-shift = <2>;
313				interrupts = <8>;
314				no-loopback-test;
315				status = "disabled";
316			};
317
318			lpc: lpc@1e789000 {
319				compatible = "aspeed,ast2500-lpc", "simple-mfd";
320				reg = <0x1e789000 0x1000>;
321
322				#address-cells = <1>;
323				#size-cells = <1>;
324				ranges = <0x0 0x1e789000 0x1000>;
325
326				lpc_bmc: lpc-bmc@0 {
327					compatible = "aspeed,ast2500-lpc-bmc";
328					reg = <0x0 0x80>;
329				};
330
331				lpc_host: lpc-host@80 {
332					compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
333					reg = <0x80 0x1e0>;
334					reg-io-width = <4>;
335
336					#address-cells = <1>;
337					#size-cells = <1>;
338					ranges = <0x0 0x80 0x1e0>;
339
340					lpc_ctrl: lpc-ctrl@0 {
341						compatible = "aspeed,ast2500-lpc-ctrl";
342						reg = <0x0 0x80>;
343						status = "disabled";
344					};
345
346					lpc_snoop: lpc-snoop@0 {
347						compatible = "aspeed,ast2500-lpc-snoop";
348						reg = <0x0 0x80>;
349						interrupts = <8>;
350						status = "disabled";
351					};
352
353					lhc: lhc@20 {
354						compatible = "aspeed,ast2500-lhc";
355						reg = <0x20 0x24 0x48 0x8>;
356					};
357
358					lpc_reset: reset-controller@18 {
359						compatible = "aspeed,ast2500-lpc-reset";
360						reg = <0x18 0x4>;
361						#reset-cells = <1>;
362					};
363
364					ibt: ibt@c0 {
365						compatible = "aspeed,ast2500-ibt-bmc";
366						reg = <0xc0 0x18>;
367						interrupts = <8>;
368						status = "disabled";
369					};
370				};
371			};
372
373			uart2: serial@1e78d000 {
374				compatible = "ns16550a";
375				reg = <0x1e78d000 0x20>;
376				reg-shift = <2>;
377				interrupts = <32>;
378				no-loopback-test;
379				status = "disabled";
380			};
381
382			uart3: serial@1e78e000 {
383				compatible = "ns16550a";
384				reg = <0x1e78e000 0x20>;
385				reg-shift = <2>;
386				interrupts = <33>;
387				no-loopback-test;
388				status = "disabled";
389			};
390
391			uart4: serial@1e78f000 {
392				compatible = "ns16550a";
393				reg = <0x1e78f000 0x20>;
394				reg-shift = <2>;
395				interrupts = <34>;
396				no-loopback-test;
397				status = "disabled";
398			};
399
400			i2c: i2c@1e78a000 {
401				compatible = "simple-bus";
402				#address-cells = <1>;
403				#size-cells = <1>;
404				ranges = <0 0x1e78a000 0x1000>;
405			};
406		};
407	};
408};
409
410&i2c {
411	i2c_ic: interrupt-controller@0 {
412		#interrupt-cells = <1>;
413		compatible = "aspeed,ast2500-i2c-ic";
414		reg = <0x0 0x40>;
415		interrupts = <12>;
416		interrupt-controller;
417	};
418
419	i2c0: i2c-bus@40 {
420		#address-cells = <1>;
421		#size-cells = <0>;
422		#interrupt-cells = <1>;
423
424		reg = <0x40 0x40>;
425		compatible = "aspeed,ast2500-i2c-bus";
426		bus-frequency = <100000>;
427		interrupts = <0>;
428		interrupt-parent = <&i2c_ic>;
429		status = "disabled";
430		/* Does not need pinctrl properties */
431	};
432
433	i2c1: i2c-bus@80 {
434		#address-cells = <1>;
435		#size-cells = <0>;
436		#interrupt-cells = <1>;
437
438		reg = <0x80 0x40>;
439		compatible = "aspeed,ast2500-i2c-bus";
440		bus-frequency = <100000>;
441		interrupts = <1>;
442		interrupt-parent = <&i2c_ic>;
443		status = "disabled";
444		/* Does not need pinctrl properties */
445	};
446
447	i2c2: i2c-bus@c0 {
448		#address-cells = <1>;
449		#size-cells = <0>;
450		#interrupt-cells = <1>;
451
452		reg = <0xc0 0x40>;
453		compatible = "aspeed,ast2500-i2c-bus";
454		bus-frequency = <100000>;
455		interrupts = <2>;
456		interrupt-parent = <&i2c_ic>;
457		pinctrl-names = "default";
458		pinctrl-0 = <&pinctrl_i2c3_default>;
459		status = "disabled";
460	};
461
462	i2c3: i2c-bus@100 {
463		#address-cells = <1>;
464		#size-cells = <0>;
465		#interrupt-cells = <1>;
466
467		reg = <0x100 0x40>;
468		compatible = "aspeed,ast2500-i2c-bus";
469		bus-frequency = <100000>;
470		interrupts = <3>;
471		interrupt-parent = <&i2c_ic>;
472		pinctrl-names = "default";
473		pinctrl-0 = <&pinctrl_i2c4_default>;
474		status = "disabled";
475	};
476
477	i2c4: i2c-bus@140 {
478		#address-cells = <1>;
479		#size-cells = <0>;
480		#interrupt-cells = <1>;
481
482		reg = <0x140 0x40>;
483		compatible = "aspeed,ast2500-i2c-bus";
484		bus-frequency = <100000>;
485		interrupts = <4>;
486		interrupt-parent = <&i2c_ic>;
487		pinctrl-names = "default";
488		pinctrl-0 = <&pinctrl_i2c5_default>;
489		status = "disabled";
490	};
491
492	i2c5: i2c-bus@180 {
493		#address-cells = <1>;
494		#size-cells = <0>;
495		#interrupt-cells = <1>;
496
497		reg = <0x180 0x40>;
498		compatible = "aspeed,ast2500-i2c-bus";
499		bus-frequency = <100000>;
500		interrupts = <5>;
501		interrupt-parent = <&i2c_ic>;
502		pinctrl-names = "default";
503		pinctrl-0 = <&pinctrl_i2c6_default>;
504		status = "disabled";
505	};
506
507	i2c6: i2c-bus@1c0 {
508		#address-cells = <1>;
509		#size-cells = <0>;
510		#interrupt-cells = <1>;
511
512		reg = <0x1c0 0x40>;
513		compatible = "aspeed,ast2500-i2c-bus";
514		bus-frequency = <100000>;
515		interrupts = <6>;
516		interrupt-parent = <&i2c_ic>;
517		pinctrl-names = "default";
518		pinctrl-0 = <&pinctrl_i2c7_default>;
519		status = "disabled";
520	};
521
522	i2c7: i2c-bus@300 {
523		#address-cells = <1>;
524		#size-cells = <0>;
525		#interrupt-cells = <1>;
526
527		reg = <0x300 0x40>;
528		compatible = "aspeed,ast2500-i2c-bus";
529		bus-frequency = <100000>;
530		interrupts = <7>;
531		interrupt-parent = <&i2c_ic>;
532		pinctrl-names = "default";
533		pinctrl-0 = <&pinctrl_i2c8_default>;
534		status = "disabled";
535	};
536
537	i2c8: i2c-bus@340 {
538		#address-cells = <1>;
539		#size-cells = <0>;
540		#interrupt-cells = <1>;
541
542		reg = <0x340 0x40>;
543		compatible = "aspeed,ast2500-i2c-bus";
544		bus-frequency = <100000>;
545		interrupts = <8>;
546		interrupt-parent = <&i2c_ic>;
547		pinctrl-names = "default";
548		pinctrl-0 = <&pinctrl_i2c9_default>;
549		status = "disabled";
550	};
551
552	i2c9: i2c-bus@380 {
553		#address-cells = <1>;
554		#size-cells = <0>;
555		#interrupt-cells = <1>;
556
557		reg = <0x380 0x40>;
558		compatible = "aspeed,ast2500-i2c-bus";
559		bus-frequency = <100000>;
560		interrupts = <9>;
561		interrupt-parent = <&i2c_ic>;
562		pinctrl-names = "default";
563		pinctrl-0 = <&pinctrl_i2c10_default>;
564		status = "disabled";
565	};
566
567	i2c10: i2c-bus@3c0 {
568		#address-cells = <1>;
569		#size-cells = <0>;
570		#interrupt-cells = <1>;
571
572		reg = <0x3c0 0x40>;
573		compatible = "aspeed,ast2500-i2c-bus";
574		bus-frequency = <100000>;
575		interrupts = <10>;
576		interrupt-parent = <&i2c_ic>;
577		pinctrl-names = "default";
578		pinctrl-0 = <&pinctrl_i2c11_default>;
579		status = "disabled";
580	};
581
582	i2c11: i2c-bus@400 {
583		#address-cells = <1>;
584		#size-cells = <0>;
585		#interrupt-cells = <1>;
586
587		reg = <0x400 0x40>;
588		compatible = "aspeed,ast2500-i2c-bus";
589		bus-frequency = <100000>;
590		interrupts = <11>;
591		interrupt-parent = <&i2c_ic>;
592		pinctrl-names = "default";
593		pinctrl-0 = <&pinctrl_i2c12_default>;
594		status = "disabled";
595	};
596
597	i2c12: i2c-bus@440 {
598		#address-cells = <1>;
599		#size-cells = <0>;
600		#interrupt-cells = <1>;
601
602		reg = <0x440 0x40>;
603		compatible = "aspeed,ast2500-i2c-bus";
604		bus-frequency = <100000>;
605		interrupts = <12>;
606		interrupt-parent = <&i2c_ic>;
607		pinctrl-names = "default";
608		pinctrl-0 = <&pinctrl_i2c13_default>;
609		status = "disabled";
610	};
611
612	i2c13: i2c-bus@480 {
613		#address-cells = <1>;
614		#size-cells = <0>;
615		#interrupt-cells = <1>;
616
617		reg = <0x480 0x40>;
618		compatible = "aspeed,ast2500-i2c-bus";
619		bus-frequency = <100000>;
620		interrupts = <13>;
621		interrupt-parent = <&i2c_ic>;
622		pinctrl-names = "default";
623		pinctrl-0 = <&pinctrl_i2c14_default>;
624		status = "disabled";
625	};
626};
627
628&pinctrl {
629	pinctrl_acpi_default: acpi_default {
630		function = "ACPI";
631		groups = "ACPI";
632	};
633
634	pinctrl_adc0_default: adc0_default {
635		function = "ADC0";
636		groups = "ADC0";
637	};
638
639	pinctrl_adc1_default: adc1_default {
640		function = "ADC1";
641		groups = "ADC1";
642	};
643
644	pinctrl_adc10_default: adc10_default {
645		function = "ADC10";
646		groups = "ADC10";
647	};
648
649	pinctrl_adc11_default: adc11_default {
650		function = "ADC11";
651		groups = "ADC11";
652	};
653
654	pinctrl_adc12_default: adc12_default {
655		function = "ADC12";
656		groups = "ADC12";
657	};
658
659	pinctrl_adc13_default: adc13_default {
660		function = "ADC13";
661		groups = "ADC13";
662	};
663
664	pinctrl_adc14_default: adc14_default {
665		function = "ADC14";
666		groups = "ADC14";
667	};
668
669	pinctrl_adc15_default: adc15_default {
670		function = "ADC15";
671		groups = "ADC15";
672	};
673
674	pinctrl_adc2_default: adc2_default {
675		function = "ADC2";
676		groups = "ADC2";
677	};
678
679	pinctrl_adc3_default: adc3_default {
680		function = "ADC3";
681		groups = "ADC3";
682	};
683
684	pinctrl_adc4_default: adc4_default {
685		function = "ADC4";
686		groups = "ADC4";
687	};
688
689	pinctrl_adc5_default: adc5_default {
690		function = "ADC5";
691		groups = "ADC5";
692	};
693
694	pinctrl_adc6_default: adc6_default {
695		function = "ADC6";
696		groups = "ADC6";
697	};
698
699	pinctrl_adc7_default: adc7_default {
700		function = "ADC7";
701		groups = "ADC7";
702	};
703
704	pinctrl_adc8_default: adc8_default {
705		function = "ADC8";
706		groups = "ADC8";
707	};
708
709	pinctrl_adc9_default: adc9_default {
710		function = "ADC9";
711		groups = "ADC9";
712	};
713
714	pinctrl_bmcint_default: bmcint_default {
715		function = "BMCINT";
716		groups = "BMCINT";
717	};
718
719	pinctrl_ddcclk_default: ddcclk_default {
720		function = "DDCCLK";
721		groups = "DDCCLK";
722	};
723
724	pinctrl_ddcdat_default: ddcdat_default {
725		function = "DDCDAT";
726		groups = "DDCDAT";
727	};
728
729	pinctrl_espi_default: espi_default {
730		function = "ESPI";
731		groups = "ESPI";
732	};
733
734	pinctrl_fwspics1_default: fwspics1_default {
735		function = "FWSPICS1";
736		groups = "FWSPICS1";
737	};
738
739	pinctrl_fwspics2_default: fwspics2_default {
740		function = "FWSPICS2";
741		groups = "FWSPICS2";
742	};
743
744	pinctrl_gpid0_default: gpid0_default {
745		function = "GPID0";
746		groups = "GPID0";
747	};
748
749	pinctrl_gpid2_default: gpid2_default {
750		function = "GPID2";
751		groups = "GPID2";
752	};
753
754	pinctrl_gpid4_default: gpid4_default {
755		function = "GPID4";
756		groups = "GPID4";
757	};
758
759	pinctrl_gpid6_default: gpid6_default {
760		function = "GPID6";
761		groups = "GPID6";
762	};
763
764	pinctrl_gpie0_default: gpie0_default {
765		function = "GPIE0";
766		groups = "GPIE0";
767	};
768
769	pinctrl_gpie2_default: gpie2_default {
770		function = "GPIE2";
771		groups = "GPIE2";
772	};
773
774	pinctrl_gpie4_default: gpie4_default {
775		function = "GPIE4";
776		groups = "GPIE4";
777	};
778
779	pinctrl_gpie6_default: gpie6_default {
780		function = "GPIE6";
781		groups = "GPIE6";
782	};
783
784	pinctrl_i2c10_default: i2c10_default {
785		function = "I2C10";
786		groups = "I2C10";
787	};
788
789	pinctrl_i2c11_default: i2c11_default {
790		function = "I2C11";
791		groups = "I2C11";
792	};
793
794	pinctrl_i2c12_default: i2c12_default {
795		function = "I2C12";
796		groups = "I2C12";
797	};
798
799	pinctrl_i2c13_default: i2c13_default {
800		function = "I2C13";
801		groups = "I2C13";
802	};
803
804	pinctrl_i2c14_default: i2c14_default {
805		function = "I2C14";
806		groups = "I2C14";
807	};
808
809	pinctrl_i2c3_default: i2c3_default {
810		function = "I2C3";
811		groups = "I2C3";
812	};
813
814	pinctrl_i2c4_default: i2c4_default {
815		function = "I2C4";
816		groups = "I2C4";
817	};
818
819	pinctrl_i2c5_default: i2c5_default {
820		function = "I2C5";
821		groups = "I2C5";
822	};
823
824	pinctrl_i2c6_default: i2c6_default {
825		function = "I2C6";
826		groups = "I2C6";
827	};
828
829	pinctrl_i2c7_default: i2c7_default {
830		function = "I2C7";
831		groups = "I2C7";
832	};
833
834	pinctrl_i2c8_default: i2c8_default {
835		function = "I2C8";
836		groups = "I2C8";
837	};
838
839	pinctrl_i2c9_default: i2c9_default {
840		function = "I2C9";
841		groups = "I2C9";
842	};
843
844	pinctrl_lad0_default: lad0_default {
845		function = "LAD0";
846		groups = "LAD0";
847	};
848
849	pinctrl_lad1_default: lad1_default {
850		function = "LAD1";
851		groups = "LAD1";
852	};
853
854	pinctrl_lad2_default: lad2_default {
855		function = "LAD2";
856		groups = "LAD2";
857	};
858
859	pinctrl_lad3_default: lad3_default {
860		function = "LAD3";
861		groups = "LAD3";
862	};
863
864	pinctrl_lclk_default: lclk_default {
865		function = "LCLK";
866		groups = "LCLK";
867	};
868
869	pinctrl_lframe_default: lframe_default {
870		function = "LFRAME";
871		groups = "LFRAME";
872	};
873
874	pinctrl_lpchc_default: lpchc_default {
875		function = "LPCHC";
876		groups = "LPCHC";
877	};
878
879	pinctrl_lpcpd_default: lpcpd_default {
880		function = "LPCPD";
881		groups = "LPCPD";
882	};
883
884	pinctrl_lpcplus_default: lpcplus_default {
885		function = "LPCPLUS";
886		groups = "LPCPLUS";
887	};
888
889	pinctrl_lpcpme_default: lpcpme_default {
890		function = "LPCPME";
891		groups = "LPCPME";
892	};
893
894	pinctrl_lpcrst_default: lpcrst_default {
895		function = "LPCRST";
896		groups = "LPCRST";
897	};
898
899	pinctrl_lpcsmi_default: lpcsmi_default {
900		function = "LPCSMI";
901		groups = "LPCSMI";
902	};
903
904	pinctrl_lsirq_default: lsirq_default {
905		function = "LSIRQ";
906		groups = "LSIRQ";
907	};
908
909	pinctrl_mac1link_default: mac1link_default {
910		function = "MAC1LINK";
911		groups = "MAC1LINK";
912	};
913
914	pinctrl_mac2link_default: mac2link_default {
915		function = "MAC2LINK";
916		groups = "MAC2LINK";
917	};
918
919	pinctrl_mdio1_default: mdio1_default {
920		function = "MDIO1";
921		groups = "MDIO1";
922	};
923
924	pinctrl_mdio2_default: mdio2_default {
925		function = "MDIO2";
926		groups = "MDIO2";
927	};
928
929	pinctrl_ncts1_default: ncts1_default {
930		function = "NCTS1";
931		groups = "NCTS1";
932	};
933
934	pinctrl_ncts2_default: ncts2_default {
935		function = "NCTS2";
936		groups = "NCTS2";
937	};
938
939	pinctrl_ncts3_default: ncts3_default {
940		function = "NCTS3";
941		groups = "NCTS3";
942	};
943
944	pinctrl_ncts4_default: ncts4_default {
945		function = "NCTS4";
946		groups = "NCTS4";
947	};
948
949	pinctrl_ndcd1_default: ndcd1_default {
950		function = "NDCD1";
951		groups = "NDCD1";
952	};
953
954	pinctrl_ndcd2_default: ndcd2_default {
955		function = "NDCD2";
956		groups = "NDCD2";
957	};
958
959	pinctrl_ndcd3_default: ndcd3_default {
960		function = "NDCD3";
961		groups = "NDCD3";
962	};
963
964	pinctrl_ndcd4_default: ndcd4_default {
965		function = "NDCD4";
966		groups = "NDCD4";
967	};
968
969	pinctrl_ndsr1_default: ndsr1_default {
970		function = "NDSR1";
971		groups = "NDSR1";
972	};
973
974	pinctrl_ndsr2_default: ndsr2_default {
975		function = "NDSR2";
976		groups = "NDSR2";
977	};
978
979	pinctrl_ndsr3_default: ndsr3_default {
980		function = "NDSR3";
981		groups = "NDSR3";
982	};
983
984	pinctrl_ndsr4_default: ndsr4_default {
985		function = "NDSR4";
986		groups = "NDSR4";
987	};
988
989	pinctrl_ndtr1_default: ndtr1_default {
990		function = "NDTR1";
991		groups = "NDTR1";
992	};
993
994	pinctrl_ndtr2_default: ndtr2_default {
995		function = "NDTR2";
996		groups = "NDTR2";
997	};
998
999	pinctrl_ndtr3_default: ndtr3_default {
1000		function = "NDTR3";
1001		groups = "NDTR3";
1002	};
1003
1004	pinctrl_ndtr4_default: ndtr4_default {
1005		function = "NDTR4";
1006		groups = "NDTR4";
1007	};
1008
1009	pinctrl_nri1_default: nri1_default {
1010		function = "NRI1";
1011		groups = "NRI1";
1012	};
1013
1014	pinctrl_nri2_default: nri2_default {
1015		function = "NRI2";
1016		groups = "NRI2";
1017	};
1018
1019	pinctrl_nri3_default: nri3_default {
1020		function = "NRI3";
1021		groups = "NRI3";
1022	};
1023
1024	pinctrl_nri4_default: nri4_default {
1025		function = "NRI4";
1026		groups = "NRI4";
1027	};
1028
1029	pinctrl_nrts1_default: nrts1_default {
1030		function = "NRTS1";
1031		groups = "NRTS1";
1032	};
1033
1034	pinctrl_nrts2_default: nrts2_default {
1035		function = "NRTS2";
1036		groups = "NRTS2";
1037	};
1038
1039	pinctrl_nrts3_default: nrts3_default {
1040		function = "NRTS3";
1041		groups = "NRTS3";
1042	};
1043
1044	pinctrl_nrts4_default: nrts4_default {
1045		function = "NRTS4";
1046		groups = "NRTS4";
1047	};
1048
1049	pinctrl_oscclk_default: oscclk_default {
1050		function = "OSCCLK";
1051		groups = "OSCCLK";
1052	};
1053
1054	pinctrl_pewake_default: pewake_default {
1055		function = "PEWAKE";
1056		groups = "PEWAKE";
1057	};
1058
1059	pinctrl_pnor_default: pnor_default {
1060		function = "PNOR";
1061		groups = "PNOR";
1062	};
1063
1064	pinctrl_pwm0_default: pwm0_default {
1065		function = "PWM0";
1066		groups = "PWM0";
1067	};
1068
1069	pinctrl_pwm1_default: pwm1_default {
1070		function = "PWM1";
1071		groups = "PWM1";
1072	};
1073
1074	pinctrl_pwm2_default: pwm2_default {
1075		function = "PWM2";
1076		groups = "PWM2";
1077	};
1078
1079	pinctrl_pwm3_default: pwm3_default {
1080		function = "PWM3";
1081		groups = "PWM3";
1082	};
1083
1084	pinctrl_pwm4_default: pwm4_default {
1085		function = "PWM4";
1086		groups = "PWM4";
1087	};
1088
1089	pinctrl_pwm5_default: pwm5_default {
1090		function = "PWM5";
1091		groups = "PWM5";
1092	};
1093
1094	pinctrl_pwm6_default: pwm6_default {
1095		function = "PWM6";
1096		groups = "PWM6";
1097	};
1098
1099	pinctrl_pwm7_default: pwm7_default {
1100		function = "PWM7";
1101		groups = "PWM7";
1102	};
1103
1104	pinctrl_rgmii1_default: rgmii1_default {
1105		function = "RGMII1";
1106		groups = "RGMII1";
1107	};
1108
1109	pinctrl_rgmii2_default: rgmii2_default {
1110		function = "RGMII2";
1111		groups = "RGMII2";
1112	};
1113
1114	pinctrl_rmii1_default: rmii1_default {
1115		function = "RMII1";
1116		groups = "RMII1";
1117	};
1118
1119	pinctrl_rmii2_default: rmii2_default {
1120		function = "RMII2";
1121		groups = "RMII2";
1122	};
1123
1124	pinctrl_rxd1_default: rxd1_default {
1125		function = "RXD1";
1126		groups = "RXD1";
1127	};
1128
1129	pinctrl_rxd2_default: rxd2_default {
1130		function = "RXD2";
1131		groups = "RXD2";
1132	};
1133
1134	pinctrl_rxd3_default: rxd3_default {
1135		function = "RXD3";
1136		groups = "RXD3";
1137	};
1138
1139	pinctrl_rxd4_default: rxd4_default {
1140		function = "RXD4";
1141		groups = "RXD4";
1142	};
1143
1144	pinctrl_salt1_default: salt1_default {
1145		function = "SALT1";
1146		groups = "SALT1";
1147	};
1148
1149	pinctrl_salt10_default: salt10_default {
1150		function = "SALT10";
1151		groups = "SALT10";
1152	};
1153
1154	pinctrl_salt11_default: salt11_default {
1155		function = "SALT11";
1156		groups = "SALT11";
1157	};
1158
1159	pinctrl_salt12_default: salt12_default {
1160		function = "SALT12";
1161		groups = "SALT12";
1162	};
1163
1164	pinctrl_salt13_default: salt13_default {
1165		function = "SALT13";
1166		groups = "SALT13";
1167	};
1168
1169	pinctrl_salt14_default: salt14_default {
1170		function = "SALT14";
1171		groups = "SALT14";
1172	};
1173
1174	pinctrl_salt2_default: salt2_default {
1175		function = "SALT2";
1176		groups = "SALT2";
1177	};
1178
1179	pinctrl_salt3_default: salt3_default {
1180		function = "SALT3";
1181		groups = "SALT3";
1182	};
1183
1184	pinctrl_salt4_default: salt4_default {
1185		function = "SALT4";
1186		groups = "SALT4";
1187	};
1188
1189	pinctrl_salt5_default: salt5_default {
1190		function = "SALT5";
1191		groups = "SALT5";
1192	};
1193
1194	pinctrl_salt6_default: salt6_default {
1195		function = "SALT6";
1196		groups = "SALT6";
1197	};
1198
1199	pinctrl_salt7_default: salt7_default {
1200		function = "SALT7";
1201		groups = "SALT7";
1202	};
1203
1204	pinctrl_salt8_default: salt8_default {
1205		function = "SALT8";
1206		groups = "SALT8";
1207	};
1208
1209	pinctrl_salt9_default: salt9_default {
1210		function = "SALT9";
1211		groups = "SALT9";
1212	};
1213
1214	pinctrl_scl1_default: scl1_default {
1215		function = "SCL1";
1216		groups = "SCL1";
1217	};
1218
1219	pinctrl_scl2_default: scl2_default {
1220		function = "SCL2";
1221		groups = "SCL2";
1222	};
1223
1224	pinctrl_sd1_default: sd1_default {
1225		function = "SD1";
1226		groups = "SD1";
1227	};
1228
1229	pinctrl_sd2_default: sd2_default {
1230		function = "SD2";
1231		groups = "SD2";
1232	};
1233
1234	pinctrl_sda1_default: sda1_default {
1235		function = "SDA1";
1236		groups = "SDA1";
1237	};
1238
1239	pinctrl_sda2_default: sda2_default {
1240		function = "SDA2";
1241		groups = "SDA2";
1242	};
1243
1244	pinctrl_sgps1_default: sgps1_default {
1245		function = "SGPS1";
1246		groups = "SGPS1";
1247	};
1248
1249	pinctrl_sgps2_default: sgps2_default {
1250		function = "SGPS2";
1251		groups = "SGPS2";
1252	};
1253
1254	pinctrl_sioonctrl_default: sioonctrl_default {
1255		function = "SIOONCTRL";
1256		groups = "SIOONCTRL";
1257	};
1258
1259	pinctrl_siopbi_default: siopbi_default {
1260		function = "SIOPBI";
1261		groups = "SIOPBI";
1262	};
1263
1264	pinctrl_siopbo_default: siopbo_default {
1265		function = "SIOPBO";
1266		groups = "SIOPBO";
1267	};
1268
1269	pinctrl_siopwreq_default: siopwreq_default {
1270		function = "SIOPWREQ";
1271		groups = "SIOPWREQ";
1272	};
1273
1274	pinctrl_siopwrgd_default: siopwrgd_default {
1275		function = "SIOPWRGD";
1276		groups = "SIOPWRGD";
1277	};
1278
1279	pinctrl_sios3_default: sios3_default {
1280		function = "SIOS3";
1281		groups = "SIOS3";
1282	};
1283
1284	pinctrl_sios5_default: sios5_default {
1285		function = "SIOS5";
1286		groups = "SIOS5";
1287	};
1288
1289	pinctrl_siosci_default: siosci_default {
1290		function = "SIOSCI";
1291		groups = "SIOSCI";
1292	};
1293
1294	pinctrl_spi1_default: spi1_default {
1295		function = "SPI1";
1296		groups = "SPI1";
1297	};
1298
1299	pinctrl_spi1cs1_default: spi1cs1_default {
1300		function = "SPI1CS1";
1301		groups = "SPI1CS1";
1302	};
1303
1304	pinctrl_spi1debug_default: spi1debug_default {
1305		function = "SPI1DEBUG";
1306		groups = "SPI1DEBUG";
1307	};
1308
1309	pinctrl_spi1passthru_default: spi1passthru_default {
1310		function = "SPI1PASSTHRU";
1311		groups = "SPI1PASSTHRU";
1312	};
1313
1314	pinctrl_spi2ck_default: spi2ck_default {
1315		function = "SPI2CK";
1316		groups = "SPI2CK";
1317	};
1318
1319	pinctrl_spi2cs0_default: spi2cs0_default {
1320		function = "SPI2CS0";
1321		groups = "SPI2CS0";
1322	};
1323
1324	pinctrl_spi2cs1_default: spi2cs1_default {
1325		function = "SPI2CS1";
1326		groups = "SPI2CS1";
1327	};
1328
1329	pinctrl_spi2miso_default: spi2miso_default {
1330		function = "SPI2MISO";
1331		groups = "SPI2MISO";
1332	};
1333
1334	pinctrl_spi2mosi_default: spi2mosi_default {
1335		function = "SPI2MOSI";
1336		groups = "SPI2MOSI";
1337	};
1338
1339	pinctrl_timer3_default: timer3_default {
1340		function = "TIMER3";
1341		groups = "TIMER3";
1342	};
1343
1344	pinctrl_timer4_default: timer4_default {
1345		function = "TIMER4";
1346		groups = "TIMER4";
1347	};
1348
1349	pinctrl_timer5_default: timer5_default {
1350		function = "TIMER5";
1351		groups = "TIMER5";
1352	};
1353
1354	pinctrl_timer6_default: timer6_default {
1355		function = "TIMER6";
1356		groups = "TIMER6";
1357	};
1358
1359	pinctrl_timer7_default: timer7_default {
1360		function = "TIMER7";
1361		groups = "TIMER7";
1362	};
1363
1364	pinctrl_timer8_default: timer8_default {
1365		function = "TIMER8";
1366		groups = "TIMER8";
1367	};
1368
1369	pinctrl_txd1_default: txd1_default {
1370		function = "TXD1";
1371		groups = "TXD1";
1372	};
1373
1374	pinctrl_txd2_default: txd2_default {
1375		function = "TXD2";
1376		groups = "TXD2";
1377	};
1378
1379	pinctrl_txd3_default: txd3_default {
1380		function = "TXD3";
1381		groups = "TXD3";
1382	};
1383
1384	pinctrl_txd4_default: txd4_default {
1385		function = "TXD4";
1386		groups = "TXD4";
1387	};
1388
1389	pinctrl_uart6_default: uart6_default {
1390		function = "UART6";
1391		groups = "UART6";
1392	};
1393
1394	pinctrl_usbcki_default: usbcki_default {
1395		function = "USBCKI";
1396		groups = "USBCKI";
1397	};
1398
1399	pinctrl_usb2ah_default: usb2ah_default {
1400		function = "USB2AH";
1401		groups = "USB2AH";
1402	};
1403
1404	pinctrl_usb11bhid_default: usb11bhid_default {
1405		function = "USB11BHID";
1406		groups = "USB11BHID";
1407	};
1408
1409	pinctrl_usb2bh_default: usb2bh_default {
1410		function = "USB2BH";
1411		groups = "USB2BH";
1412	};
1413
1414	pinctrl_vgabiosrom_default: vgabiosrom_default {
1415		function = "VGABIOSROM";
1416		groups = "VGABIOSROM";
1417	};
1418
1419	pinctrl_vgahs_default: vgahs_default {
1420		function = "VGAHS";
1421		groups = "VGAHS";
1422	};
1423
1424	pinctrl_vgavs_default: vgavs_default {
1425		function = "VGAVS";
1426		groups = "VGAVS";
1427	};
1428
1429	pinctrl_vpi24_default: vpi24_default {
1430		function = "VPI24";
1431		groups = "VPI24";
1432	};
1433
1434	pinctrl_vpo_default: vpo_default {
1435		function = "VPO";
1436		groups = "VPO";
1437	};
1438
1439	pinctrl_wdtrst1_default: wdtrst1_default {
1440		function = "WDTRST1";
1441		groups = "WDTRST1";
1442	};
1443
1444	pinctrl_wdtrst2_default: wdtrst2_default {
1445		function = "WDTRST2";
1446		groups = "WDTRST2";
1447	};
1448};
1449