1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	arm-pmu {
26		compatible = "arm,cortex-a7-pmu";
27		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
28		interrupt-affinity = <&cpu0>;
29		interrupt-parent = <&intc>;
30	};
31
32	firmware {
33		optee {
34			method = "smc";
35			compatible = "linaro,optee-tz";
36		};
37
38		scmi: scmi {
39			compatible = "linaro,scmi-optee";
40			#address-cells = <1>;
41			#size-cells = <0>;
42			linaro,optee-channel-id = <0>;
43			shmem = <&scmi_shm>;
44
45			scmi_clk: protocol@14 {
46				reg = <0x14>;
47				#clock-cells = <1>;
48			};
49
50			scmi_reset: protocol@16 {
51				reg = <0x16>;
52				#reset-cells = <1>;
53			};
54		};
55	};
56
57	intc: interrupt-controller@a0021000 {
58		compatible = "arm,cortex-a7-gic";
59		#interrupt-cells = <3>;
60		interrupt-controller;
61		reg = <0xa0021000 0x1000>,
62		      <0xa0022000 0x2000>;
63	};
64
65	psci {
66		compatible = "arm,psci-1.0";
67		method = "smc";
68	};
69
70	timer {
71		compatible = "arm,armv7-timer";
72		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
73			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
74			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
76		interrupt-parent = <&intc>;
77		always-on;
78	};
79
80	soc {
81		compatible = "simple-bus";
82		#address-cells = <1>;
83		#size-cells = <1>;
84		interrupt-parent = <&intc>;
85		ranges;
86
87		scmi_sram: sram@2ffff000 {
88			compatible = "mmio-sram";
89			reg = <0x2ffff000 0x1000>;
90			#address-cells = <1>;
91			#size-cells = <1>;
92			ranges = <0 0x2ffff000 0x1000>;
93
94			scmi_shm: scmi-sram@0 {
95				compatible = "arm,scmi-shmem";
96				reg = <0 0x80>;
97			};
98		};
99
100		uart4: serial@40010000 {
101			compatible = "st,stm32h7-uart";
102			reg = <0x40010000 0x400>;
103			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
104			clocks = <&rcc UART4_K>;
105			resets = <&rcc UART4_R>;
106			status = "disabled";
107		};
108
109		dma1: dma-controller@48000000 {
110			compatible = "st,stm32-dma";
111			reg = <0x48000000 0x400>;
112			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
113				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
114				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
115				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
116				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
117				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
118				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
119				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
120			clocks = <&rcc DMA1>;
121			resets = <&rcc DMA1_R>;
122			#dma-cells = <4>;
123			st,mem2mem;
124			dma-requests = <8>;
125		};
126
127		dma2: dma-controller@48001000 {
128			compatible = "st,stm32-dma";
129			reg = <0x48001000 0x400>;
130			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
131				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
132				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
133				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
134				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
135				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
136				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
137				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
138			clocks = <&rcc DMA2>;
139			resets = <&rcc DMA2_R>;
140			#dma-cells = <4>;
141			st,mem2mem;
142			dma-requests = <8>;
143		};
144
145		dmamux1: dma-router@48002000 {
146			compatible = "st,stm32h7-dmamux";
147			reg = <0x48002000 0x40>;
148			clocks = <&rcc DMAMUX1>;
149			resets = <&rcc DMAMUX1_R>;
150			#dma-cells = <3>;
151			dma-masters = <&dma1 &dma2>;
152			dma-requests = <128>;
153			dma-channels = <16>;
154		};
155
156		rcc: rcc@50000000 {
157			compatible = "st,stm32mp13-rcc", "syscon";
158			reg = <0x50000000 0x1000>;
159			#clock-cells = <1>;
160			#reset-cells = <1>;
161			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
162
163			clock-names = "hse", "hsi", "csi", "lse", "lsi";
164			clocks = <&scmi_clk CK_SCMI_HSE>,
165				 <&scmi_clk CK_SCMI_HSI>,
166				 <&scmi_clk CK_SCMI_CSI>,
167				 <&scmi_clk CK_SCMI_LSE>,
168				 <&scmi_clk CK_SCMI_LSI>;
169		};
170
171		exti: interrupt-controller@5000d000 {
172			compatible = "st,stm32mp13-exti", "syscon";
173			interrupt-controller;
174			#interrupt-cells = <2>;
175			reg = <0x5000d000 0x400>;
176		};
177
178		syscfg: syscon@50020000 {
179			compatible = "st,stm32mp157-syscfg", "syscon";
180			reg = <0x50020000 0x400>;
181			clocks = <&rcc SYSCFG>;
182		};
183
184		mdma: dma-controller@58000000 {
185			compatible = "st,stm32h7-mdma";
186			reg = <0x58000000 0x1000>;
187			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
188			clocks = <&rcc MDMA>;
189			#dma-cells = <5>;
190			dma-channels = <32>;
191			dma-requests = <48>;
192		};
193
194		fmc: memory-controller@58002000 {
195			compatible = "st,stm32mp1-fmc2-ebi";
196			reg = <0x58002000 0x1000>;
197			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
198				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
199				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
200				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
201				 <4 0 0x80000000 0x10000000>; /* NAND */
202			#address-cells = <2>;
203			#size-cells = <1>;
204			clocks = <&rcc FMC_K>;
205			resets = <&rcc FMC_R>;
206			status = "disabled";
207
208			nand-controller@4,0 {
209				compatible = "st,stm32mp1-fmc2-nfc";
210				reg = <4 0x00000000 0x1000>,
211				      <4 0x08010000 0x1000>,
212				      <4 0x08020000 0x1000>,
213				      <4 0x01000000 0x1000>,
214				      <4 0x09010000 0x1000>,
215				      <4 0x09020000 0x1000>;
216				#address-cells = <1>;
217				#size-cells = <0>;
218				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
219				dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
220				       <&mdma 24 0x2 0x12000a08 0x0 0x0>,
221				       <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
222				dma-names = "tx", "rx", "ecc";
223				status = "disabled";
224			};
225		};
226
227		qspi: spi@58003000 {
228			compatible = "st,stm32f469-qspi";
229			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
230			reg-names = "qspi", "qspi_mm";
231			#address-cells = <1>;
232			#size-cells = <0>;
233			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
234			dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
235			       <&mdma 26 0x2 0x10100008 0x0 0x0>;
236			dma-names = "tx", "rx";
237			clocks = <&rcc QSPI_K>;
238			resets = <&rcc QSPI_R>;
239			status = "disabled";
240		};
241
242		sdmmc1: mmc@58005000 {
243			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
244			arm,primecell-periphid = <0x20253180>;
245			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
246			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
247			clocks = <&rcc SDMMC1_K>;
248			clock-names = "apb_pclk";
249			resets = <&rcc SDMMC1_R>;
250			cap-sd-highspeed;
251			cap-mmc-highspeed;
252			max-frequency = <130000000>;
253			status = "disabled";
254		};
255
256		sdmmc2: mmc@58007000 {
257			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
258			arm,primecell-periphid = <0x20253180>;
259			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
260			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
261			clocks = <&rcc SDMMC2_K>;
262			clock-names = "apb_pclk";
263			resets = <&rcc SDMMC2_R>;
264
265			cap-sd-highspeed;
266			cap-mmc-highspeed;
267			max-frequency = <130000000>;
268			status = "disabled";
269		};
270
271		iwdg2: watchdog@5a002000 {
272			compatible = "st,stm32mp1-iwdg";
273			reg = <0x5a002000 0x400>;
274			clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
275			clock-names = "pclk", "lsi";
276			status = "disabled";
277		};
278
279		rtc: rtc@5c004000 {
280			compatible = "st,stm32mp1-rtc";
281			reg = <0x5c004000 0x400>;
282			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
283			clocks = <&scmi_clk CK_SCMI_RTCAPB>,
284				 <&scmi_clk CK_SCMI_RTC>;
285			clock-names = "pclk", "rtc_ck";
286			status = "disabled";
287		};
288
289		bsec: efuse@5c005000 {
290			compatible = "st,stm32mp13-bsec";
291			reg = <0x5c005000 0x400>;
292			#address-cells = <1>;
293			#size-cells = <1>;
294
295			part_number_otp: part_number_otp@4 {
296				reg = <0x4 0x2>;
297			};
298			ts_cal1: calib@5c {
299				reg = <0x5c 0x2>;
300			};
301			ts_cal2: calib@5e {
302				reg = <0x5e 0x2>;
303			};
304		};
305
306		/*
307		 * Break node order to solve dependency probe issue between
308		 * pinctrl and exti.
309		 */
310		pinctrl: pinctrl@50002000 {
311			#address-cells = <1>;
312			#size-cells = <1>;
313			compatible = "st,stm32mp135-pinctrl";
314			ranges = <0 0x50002000 0x8400>;
315			interrupt-parent = <&exti>;
316			st,syscfg = <&exti 0x60 0xff>;
317			pins-are-numbered;
318
319			gpioa: gpio@50002000 {
320				gpio-controller;
321				#gpio-cells = <2>;
322				interrupt-controller;
323				#interrupt-cells = <2>;
324				reg = <0x0 0x400>;
325				clocks = <&rcc GPIOA>;
326				st,bank-name = "GPIOA";
327				ngpios = <16>;
328				gpio-ranges = <&pinctrl 0 0 16>;
329			};
330
331			gpiob: gpio@50003000 {
332				gpio-controller;
333				#gpio-cells = <2>;
334				interrupt-controller;
335				#interrupt-cells = <2>;
336				reg = <0x1000 0x400>;
337				clocks = <&rcc GPIOB>;
338				st,bank-name = "GPIOB";
339				ngpios = <16>;
340				gpio-ranges = <&pinctrl 0 16 16>;
341			};
342
343			gpioc: gpio@50004000 {
344				gpio-controller;
345				#gpio-cells = <2>;
346				interrupt-controller;
347				#interrupt-cells = <2>;
348				reg = <0x2000 0x400>;
349				clocks = <&rcc GPIOC>;
350				st,bank-name = "GPIOC";
351				ngpios = <16>;
352				gpio-ranges = <&pinctrl 0 32 16>;
353			};
354
355			gpiod: gpio@50005000 {
356				gpio-controller;
357				#gpio-cells = <2>;
358				interrupt-controller;
359				#interrupt-cells = <2>;
360				reg = <0x3000 0x400>;
361				clocks = <&rcc GPIOD>;
362				st,bank-name = "GPIOD";
363				ngpios = <16>;
364				gpio-ranges = <&pinctrl 0 48 16>;
365			};
366
367			gpioe: gpio@50006000 {
368				gpio-controller;
369				#gpio-cells = <2>;
370				interrupt-controller;
371				#interrupt-cells = <2>;
372				reg = <0x4000 0x400>;
373				clocks = <&rcc GPIOE>;
374				st,bank-name = "GPIOE";
375				ngpios = <16>;
376				gpio-ranges = <&pinctrl 0 64 16>;
377			};
378
379			gpiof: gpio@50007000 {
380				gpio-controller;
381				#gpio-cells = <2>;
382				interrupt-controller;
383				#interrupt-cells = <2>;
384				reg = <0x5000 0x400>;
385				clocks = <&rcc GPIOF>;
386				st,bank-name = "GPIOF";
387				ngpios = <16>;
388				gpio-ranges = <&pinctrl 0 80 16>;
389			};
390
391			gpiog: gpio@50008000 {
392				gpio-controller;
393				#gpio-cells = <2>;
394				interrupt-controller;
395				#interrupt-cells = <2>;
396				reg = <0x6000 0x400>;
397				clocks = <&rcc GPIOG>;
398				st,bank-name = "GPIOG";
399				ngpios = <16>;
400				gpio-ranges = <&pinctrl 0 96 16>;
401			};
402
403			gpioh: gpio@50009000 {
404				gpio-controller;
405				#gpio-cells = <2>;
406				interrupt-controller;
407				#interrupt-cells = <2>;
408				reg = <0x7000 0x400>;
409				clocks = <&rcc GPIOH>;
410				st,bank-name = "GPIOH";
411				ngpios = <15>;
412				gpio-ranges = <&pinctrl 0 112 15>;
413			};
414
415			gpioi: gpio@5000a000 {
416				gpio-controller;
417				#gpio-cells = <2>;
418				interrupt-controller;
419				#interrupt-cells = <2>;
420				reg = <0x8000 0x400>;
421				clocks = <&rcc GPIOI>;
422				st,bank-name = "GPIOI";
423				ngpios = <8>;
424				gpio-ranges = <&pinctrl 0 128 8>;
425			};
426		};
427	};
428};
429