1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp15-u-boot.dtsi"
8#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
9
10/ {
11	aliases {
12		i2c3 = &i2c4;
13	};
14
15	config {
16		u-boot,boot-led = "heartbeat";
17		u-boot,error-led = "error";
18		u-boot,mmc-env-partition = "fip";
19		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
20		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
21	};
22
23#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
24	config {
25		u-boot,mmc-env-partition = "ssbl";
26	};
27#endif
28
29#ifdef CONFIG_STM32MP15x_STM32IMAGE
30	/* only needed for boot with TF-A, witout FIP support */
31	firmware {
32		optee {
33			compatible = "linaro,optee-tz";
34			method = "smc";
35		};
36	};
37
38	reserved-memory {
39		optee@fe000000 {
40			reg = <0xfe000000 0x02000000>;
41			no-map;
42		};
43	};
44#endif
45
46	led {
47		red {
48			label = "error";
49			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
50			default-state = "off";
51			status = "okay";
52		};
53	};
54};
55
56&clk_hse {
57	st,digbypass;
58};
59
60&i2c4 {
61	bootph-all;
62};
63
64&i2c4_pins_a {
65	bootph-all;
66	pins {
67		bootph-all;
68	};
69};
70
71&pmic {
72	bootph-all;
73};
74
75&rcc {
76	st,clksrc = <
77		CLK_MPU_PLL1P
78		CLK_AXI_PLL2P
79		CLK_MCU_PLL3P
80		CLK_PLL12_HSE
81		CLK_PLL3_HSE
82		CLK_PLL4_HSE
83		CLK_RTC_LSE
84		CLK_MCO1_DISABLED
85		CLK_MCO2_DISABLED
86	>;
87
88	st,clkdiv = <
89		1 /*MPU*/
90		0 /*AXI*/
91		0 /*MCU*/
92		1 /*APB1*/
93		1 /*APB2*/
94		1 /*APB3*/
95		1 /*APB4*/
96		2 /*APB5*/
97		23 /*RTC*/
98		0 /*MCO1*/
99		0 /*MCO2*/
100	>;
101
102	st,pkcs = <
103		CLK_CKPER_HSE
104		CLK_FMC_ACLK
105		CLK_QSPI_ACLK
106		CLK_ETH_DISABLED
107		CLK_SDMMC12_PLL4P
108		CLK_DSI_DSIPLL
109		CLK_STGEN_HSE
110		CLK_USBPHY_HSE
111		CLK_SPI2S1_PLL3Q
112		CLK_SPI2S23_PLL3Q
113		CLK_SPI45_HSI
114		CLK_SPI6_HSI
115		CLK_I2C46_HSI
116		CLK_SDMMC3_PLL4P
117		CLK_USBO_USBPHY
118		CLK_ADC_CKPER
119		CLK_CEC_LSE
120		CLK_I2C12_HSI
121		CLK_I2C35_HSI
122		CLK_UART1_HSI
123		CLK_UART24_HSI
124		CLK_UART35_HSI
125		CLK_UART6_HSI
126		CLK_UART78_HSI
127		CLK_SPDIF_PLL4P
128		CLK_FDCAN_PLL4R
129		CLK_SAI1_PLL3Q
130		CLK_SAI2_PLL3Q
131		CLK_SAI3_PLL3Q
132		CLK_SAI4_PLL3Q
133		CLK_RNG1_LSI
134		CLK_RNG2_LSI
135		CLK_LPTIM1_PCLK1
136		CLK_LPTIM23_PCLK3
137		CLK_LPTIM45_LSE
138	>;
139
140	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
141	pll2: st,pll@1 {
142		compatible = "st,stm32mp1-pll";
143		reg = <1>;
144		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
145		frac = < 0x1400 >;
146		bootph-all;
147	};
148
149	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
150	pll3: st,pll@2 {
151		compatible = "st,stm32mp1-pll";
152		reg = <2>;
153		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
154		frac = < 0x1a04 >;
155		bootph-all;
156	};
157
158	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
159	pll4: st,pll@3 {
160		compatible = "st,stm32mp1-pll";
161		reg = <3>;
162		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
163		bootph-all;
164	};
165};
166
167&sdmmc1 {
168	bootph-pre-ram;
169};
170
171&sdmmc1_b4_pins_a {
172	bootph-pre-ram;
173	pins1 {
174		bootph-pre-ram;
175	};
176	pins2 {
177		bootph-pre-ram;
178	};
179};
180
181&sdmmc1_dir_pins_a {
182	bootph-pre-ram;
183	pins1 {
184		bootph-pre-ram;
185	};
186	pins2 {
187		bootph-pre-ram;
188	};
189};
190
191&sdmmc2 {
192	bootph-pre-ram;
193};
194
195&sdmmc2_b4_pins_a {
196	bootph-pre-ram;
197	pins1 {
198		bootph-pre-ram;
199	};
200	pins2 {
201		bootph-pre-ram;
202	};
203};
204
205&sdmmc2_d47_pins_a {
206	bootph-pre-ram;
207	pins {
208		bootph-pre-ram;
209	};
210};
211
212&uart4 {
213	bootph-all;
214};
215
216&uart4_pins_a {
217	bootph-all;
218	pins1 {
219		bootph-all;
220	};
221	pins2 {
222		bootph-all;
223		/* pull-up on rx to avoid floating level */
224		bias-pull-up;
225	};
226};
227