1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2019 Marek Vasut <marex@denx.de>
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp15-u-boot.dtsi"
8#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
9#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
10#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
11
12/ {
13	aliases {
14		i2c1 = &i2c2;
15		i2c3 = &i2c4;
16		i2c4 = &i2c5;
17		mmc0 = &sdmmc1;
18		mmc1 = &sdmmc2;
19		spi0 = &qspi;
20		usb0 = &usbotg_hs;
21		eeprom0 = &eeprom0;
22	};
23
24	config {
25		u-boot,boot-led = "heartbeat";
26		u-boot,error-led = "error";
27		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
28		dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
29	};
30};
31
32&ethernet0 {
33	phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
34	/delete-property/ st,eth-ref-clk-sel;
35};
36
37&ethernet0_rmii_pins_a {
38	pins1 {
39		pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
40			 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
41			 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
42			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
43			 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
44			 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
45	};
46};
47
48&i2c4 {
49	bootph-all;
50	bootph-pre-ram;
51
52	eeprom0: eeprom@50 {
53	};
54};
55
56&i2c4_pins_a {
57	bootph-all;
58	pins {
59		bootph-all;
60	};
61};
62
63&phy0 {
64	/delete-property/ reset-gpios;
65};
66
67&pinctrl {
68	mco2_pins_a: mco2-0 {
69		pins {
70			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
71			bias-disable;
72			drive-push-pull;
73			slew-rate = <2>;
74		};
75	};
76
77	mco2_sleep_pins_a: mco2-sleep-0 {
78		pins {
79			pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
80		};
81	};
82};
83
84&pmic {
85	bootph-all;
86	bootph-pre-ram;
87
88	regulators {
89		bootph-pre-ram;
90	};
91};
92
93&flash0 {
94	bootph-pre-ram;
95};
96
97&qspi {
98	bootph-pre-ram;
99};
100
101&qspi_clk_pins_a {
102	bootph-pre-ram;
103	pins {
104		bootph-pre-ram;
105	};
106};
107
108&qspi_bk1_pins_a {
109	bootph-pre-ram;
110	pins1 {
111		bootph-pre-ram;
112	};
113	pins2 {
114		bootph-pre-ram;
115	};
116};
117
118&qspi_bk2_pins_a {
119	bootph-pre-ram;
120	pins1 {
121		bootph-pre-ram;
122	};
123	pins2 {
124		bootph-pre-ram;
125	};
126};
127
128&rcc {
129	st,clksrc = <
130		CLK_MPU_PLL1P
131		CLK_AXI_PLL2P
132		CLK_MCU_PLL3P
133		CLK_PLL12_HSE
134		CLK_PLL3_HSE
135		CLK_PLL4_HSE
136		CLK_RTC_LSE
137		CLK_MCO1_DISABLED
138		CLK_MCO2_PLL4P
139	>;
140
141	st,clkdiv = <
142		1 /*MPU*/
143		0 /*AXI*/
144		0 /*MCU*/
145		1 /*APB1*/
146		1 /*APB2*/
147		1 /*APB3*/
148		1 /*APB4*/
149		2 /*APB5*/
150		23 /*RTC*/
151		0 /*MCO1*/
152		1 /*MCO2*/
153	>;
154
155	st,pkcs = <
156		CLK_CKPER_HSE
157		CLK_FMC_ACLK
158		CLK_QSPI_ACLK
159		CLK_ETH_PLL4P
160		CLK_SDMMC12_PLL4P
161		CLK_DSI_DSIPLL
162		CLK_STGEN_HSE
163		CLK_USBPHY_HSE
164		CLK_SPI2S1_PLL3Q
165		CLK_SPI2S23_PLL3Q
166		CLK_SPI45_HSI
167		CLK_SPI6_HSI
168		CLK_I2C46_HSI
169		CLK_SDMMC3_PLL4P
170		CLK_USBO_USBPHY
171		CLK_ADC_CKPER
172		CLK_CEC_LSE
173		CLK_I2C12_HSI
174		CLK_I2C35_HSI
175		CLK_UART1_HSI
176		CLK_UART24_HSI
177		CLK_UART35_HSI
178		CLK_UART6_HSI
179		CLK_UART78_HSI
180		CLK_SPDIF_PLL4P
181		CLK_FDCAN_PLL4R
182		CLK_SAI1_PLL3Q
183		CLK_SAI2_PLL3Q
184		CLK_SAI3_PLL3Q
185		CLK_SAI4_PLL3Q
186		CLK_RNG1_LSI
187		CLK_RNG2_LSI
188		CLK_LPTIM1_PCLK1
189		CLK_LPTIM23_PCLK3
190		CLK_LPTIM45_LSE
191	>;
192
193	/*
194	 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
195	 * frac = < f >;
196	 *
197	 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
198	 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
199	 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
200	 * XTAL = 24 MHz
201	 *
202	 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
203	 *   P = VCO / (P + 1)
204	 *   Q = VCO / (Q + 1)
205	 *   R = VCO / (R + 1)
206	 */
207
208	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
209	pll2: st,pll@1 {
210		compatible = "st,stm32mp1-pll";
211		reg = <1>;
212		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
213		frac = < 0x1400 >;
214		bootph-all;
215	};
216
217	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
218	pll3: st,pll@2 {
219		compatible = "st,stm32mp1-pll";
220		reg = <2>;
221		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
222		frac = < 0x1a04 >;
223		bootph-all;
224	};
225
226	/* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
227	pll4: st,pll@3 {
228		compatible = "st,stm32mp1-pll";
229		reg = <3>;
230		cfg = < 1 49 5 11 11 PQR(1,1,1) >;
231		bootph-all;
232	};
233};
234
235&sdmmc1 {
236	bootph-pre-ram;
237	st,use-ckin;
238	st,cmd-gpios = <&gpiod 2 0>;
239	st,ck-gpios = <&gpioc 12 0>;
240	st,ckin-gpios = <&gpioe 4 0>;
241};
242
243&sdmmc1_b4_pins_a {
244	bootph-pre-ram;
245	pins1 {
246		bootph-pre-ram;
247	};
248	pins2 {
249		bootph-pre-ram;
250	};
251};
252
253&sdmmc1_dir_pins_a {
254	bootph-pre-ram;
255	pins1 {
256		bootph-pre-ram;
257	};
258	pins2 {
259		bootph-pre-ram;
260	};
261};
262
263&sdmmc2 {
264	bootph-pre-ram;
265};
266
267&sdmmc2_b4_pins_a {
268	bootph-pre-ram;
269	pins {
270		bootph-pre-ram;
271	};
272};
273
274&sdmmc2_d47_pins_a {
275	bootph-pre-ram;
276	pins {
277		bootph-pre-ram;
278	};
279};
280
281&uart4 {
282	bootph-all;
283};
284
285&uart4_pins_a {
286	bootph-all;
287	pins1 {
288		bootph-all;
289	};
290	pins2 {
291		bootph-all;
292		/* pull-up on rx to avoid floating level */
293		bias-pull-up;
294	};
295};
296
297&reg11 {
298	bootph-pre-ram;
299};
300
301&reg18 {
302	bootph-pre-ram;
303};
304
305&usb33 {
306	bootph-pre-ram;
307};
308
309&usbotg_hs_pins_a {
310	bootph-pre-ram;
311};
312
313&usbotg_hs {
314	bootph-pre-ram;
315};
316
317&usbphyc {
318	bootph-pre-ram;
319};
320
321&usbphyc_port0 {
322	bootph-pre-ram;
323};
324
325&usbphyc_port1 {
326	bootph-pre-ram;
327};
328
329&vdd_usb {
330	bootph-pre-ram;
331};
332