1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
11#include "stm32mp15-u-boot.dtsi"
12#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
13#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
14#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
15
16/ {
17	bootph-all;
18
19	aliases {
20		eeprom0 = &eeprom0;
21	};
22
23	config {
24		dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
25		dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
26	};
27};
28
29&flash0 {
30	bootph-pre-ram;
31};
32
33&i2c4 {
34	bootph-all;
35	bootph-pre-ram;
36
37	eeprom0: eeprom@53 {
38	};
39};
40
41&i2c4_pins_a {
42	bootph-all;
43	pins {
44		bootph-all;
45	};
46};
47
48&pmic {
49	bootph-all;
50	bootph-pre-ram;
51
52	regulators {
53		bootph-pre-ram;
54	};
55};
56
57&pwr_regulators {
58	bootph-pre-ram;
59};
60
61&qspi {
62	bootph-pre-ram;
63};
64
65&qspi_clk_pins_a {
66	bootph-pre-ram;
67	pins {
68		bootph-pre-ram;
69	};
70};
71
72&qspi_bk1_pins_a {
73	bootph-pre-ram;
74	pins1 {
75		bootph-pre-ram;
76	};
77	pins2 {
78		bootph-pre-ram;
79	};
80};
81
82&rcc {
83	st,clksrc = <
84		CLK_MPU_PLL1P
85		CLK_AXI_PLL2P
86		CLK_MCU_PLL3P
87		CLK_PLL12_HSE
88		CLK_PLL3_HSE
89		CLK_PLL4_HSE
90		CLK_RTC_LSE
91		CLK_MCO1_DISABLED
92		CLK_MCO2_DISABLED
93	>;
94
95	st,clkdiv = <
96		1 /*MPU*/
97		0 /*AXI*/
98		0 /*MCU*/
99		1 /*APB1*/
100		1 /*APB2*/
101		1 /*APB3*/
102		1 /*APB4*/
103		2 /*APB5*/
104		23 /*RTC*/
105		0 /*MCO1*/
106		0 /*MCO2*/
107	>;
108
109	st,pkcs = <
110		CLK_CKPER_HSE
111		CLK_FMC_ACLK
112		CLK_QSPI_ACLK
113		CLK_ETH_DISABLED
114		CLK_SDMMC12_PLL4P
115		CLK_DSI_DSIPLL
116		CLK_STGEN_HSE
117		CLK_USBPHY_HSE
118		CLK_SPI2S1_PLL3Q
119		CLK_SPI2S23_PLL3Q
120		CLK_SPI45_HSI
121		CLK_SPI6_HSI
122		CLK_I2C46_HSI
123		CLK_SDMMC3_PLL4P
124		CLK_USBO_USBPHY
125		CLK_ADC_CKPER
126		CLK_CEC_LSE
127		CLK_I2C12_HSI
128		CLK_I2C35_HSI
129		CLK_UART1_HSI
130		CLK_UART24_HSI
131		CLK_UART35_HSI
132		CLK_UART6_HSI
133		CLK_UART78_HSI
134		CLK_SPDIF_PLL4P
135		CLK_FDCAN_PLL4R
136		CLK_SAI1_PLL3Q
137		CLK_SAI2_PLL3Q
138		CLK_SAI3_PLL3Q
139		CLK_SAI4_PLL3Q
140		CLK_RNG1_LSI
141		CLK_RNG2_LSI
142		CLK_LPTIM1_PCLK1
143		CLK_LPTIM23_PCLK3
144		CLK_LPTIM45_LSE
145	>;
146
147	/*
148	 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
149	 * frac = < f >;
150	 *
151	 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
152	 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
153	 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
154	 * XTAL = 24 MHz
155	 *
156	 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
157	 *   P = VCO / (P + 1)
158	 *   Q = VCO / (Q + 1)
159	 *   R = VCO / (R + 1)
160	 */
161
162	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
163	pll2: st,pll@1 {
164		compatible = "st,stm32mp1-pll";
165		reg = <1>;
166		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
167		frac = < 0x1400 >;
168		bootph-all;
169	};
170
171	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
172	pll3: st,pll@2 {
173		compatible = "st,stm32mp1-pll";
174		reg = <2>;
175		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
176		frac = < 0x1a04 >;
177		bootph-all;
178	};
179
180	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
181	pll4: st,pll@3 {
182		compatible = "st,stm32mp1-pll";
183		reg = <3>;
184		cfg = < 3 98 5 7 5 PQR(1,1,1) >;
185		bootph-all;
186	};
187};
188
189&reg11 {
190	bootph-pre-ram;
191};
192
193&reg18 {
194	bootph-pre-ram;
195};
196
197&usb33 {
198	bootph-pre-ram;
199};
200
201&usbotg_hs_pins_a {
202	bootph-pre-ram;
203};
204
205&usbotg_hs {
206	bootph-pre-ram;
207};
208
209&usbphyc {
210	bootph-pre-ram;
211};
212
213&usbphyc_port0 {
214	bootph-pre-ram;
215};
216
217&usbphyc_port1 {
218	bootph-pre-ram;
219};
220
221&vdd_usb {
222	bootph-pre-ram;
223};
224