1/** @file 2 * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-2-Clause-Patent 5 */ 6 7/* These are added for U-Boot to avoid compilation error */ 8#define PcdNetsecEepromBase 0x08080000 9#define FixedPcdGet32(n) n 10 11#define GIC_SPI 0 12#define GIC_PPI 1 13 14#define IRQ_TYPE_NONE 0 15#define IRQ_TYPE_EDGE_RISING 1 16#define IRQ_TYPE_EDGE_FALLING 2 17#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 18#define IRQ_TYPE_LEVEL_HIGH 4 19#define IRQ_TYPE_LEVEL_LOW 8 20 21#define GPIO_ACTIVE_HIGH 0 22#define GPIO_ACTIVE_LOW 1 23 24/ { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 interrupt-parent = <&gic>; 28 29 aliases { 30 serial0 = &soc_uart0; 31 serial1 = &fuart; 32 }; 33 34 chosen { 35 stdout-path = "serial0:115200n8"; 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 CPU0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53"; 45 reg = <0x0>; 46 enable-method = "psci"; 47 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 48 }; 49 CPU1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x1>; 53 enable-method = "psci"; 54 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 55 }; 56 CPU2: cpu@100 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x100>; 60 enable-method = "psci"; 61 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 62 }; 63 CPU3: cpu@101 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x101>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 69 }; 70 CPU4: cpu@200 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x200>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 76 }; 77 CPU5: cpu@201 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x201>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 83 }; 84 CPU6: cpu@300 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x300>; 88 enable-method = "psci"; 89 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 90 }; 91 CPU7: cpu@301 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x301>; 95 enable-method = "psci"; 96 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 97 }; 98 CPU8: cpu@400 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x400>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 104 }; 105 CPU9: cpu@401 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x401>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 111 }; 112 CPU10: cpu@500 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a53"; 115 reg = <0x500>; 116 enable-method = "psci"; 117 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 118 }; 119 CPU11: cpu@501 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a53"; 122 reg = <0x501>; 123 enable-method = "psci"; 124 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 125 }; 126 CPU12: cpu@600 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a53"; 129 reg = <0x600>; 130 enable-method = "psci"; 131 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 132 }; 133 CPU13: cpu@601 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x601>; 137 enable-method = "psci"; 138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 139 }; 140 CPU14: cpu@700 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a53"; 143 reg = <0x700>; 144 enable-method = "psci"; 145 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 146 }; 147 CPU15: cpu@701 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a53"; 150 reg = <0x701>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 153 }; 154 CPU16: cpu@800 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a53"; 157 reg = <0x800>; 158 enable-method = "psci"; 159 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 160 }; 161 CPU17: cpu@801 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a53"; 164 reg = <0x801>; 165 enable-method = "psci"; 166 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 167 }; 168 CPU18: cpu@900 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a53"; 171 reg = <0x900>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 }; 175 CPU19: cpu@901 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a53"; 178 reg = <0x901>; 179 enable-method = "psci"; 180 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 181 }; 182 CPU20: cpu@a00 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53"; 185 reg = <0xa00>; 186 enable-method = "psci"; 187 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 188 }; 189 CPU21: cpu@a01 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a53"; 192 reg = <0xa01>; 193 enable-method = "psci"; 194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 195 }; 196 CPU22: cpu@b00 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a53"; 199 reg = <0xb00>; 200 enable-method = "psci"; 201 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 202 }; 203 CPU23: cpu@b01 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a53"; 206 reg = <0xb01>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 core1 { 217 cpu = <&CPU1>; 218 }; 219 }; 220 cluster1 { 221 core0 { 222 cpu = <&CPU2>; 223 }; 224 core1 { 225 cpu = <&CPU3>; 226 }; 227 }; 228 cluster2 { 229 core0 { 230 cpu = <&CPU4>; 231 }; 232 core1 { 233 cpu = <&CPU5>; 234 }; 235 }; 236 cluster3 { 237 core0 { 238 cpu = <&CPU6>; 239 }; 240 core1 { 241 cpu = <&CPU7>; 242 }; 243 }; 244 cluster4 { 245 core0 { 246 cpu = <&CPU8>; 247 }; 248 core1 { 249 cpu = <&CPU9>; 250 }; 251 }; 252 cluster5 { 253 core0 { 254 cpu = <&CPU10>; 255 }; 256 core1 { 257 cpu = <&CPU11>; 258 }; 259 }; 260 cluster6 { 261 core0 { 262 cpu = <&CPU12>; 263 }; 264 core1 { 265 cpu = <&CPU13>; 266 }; 267 }; 268 cluster7 { 269 core0 { 270 cpu = <&CPU14>; 271 }; 272 core1 { 273 cpu = <&CPU15>; 274 }; 275 }; 276 cluster8 { 277 core0 { 278 cpu = <&CPU16>; 279 }; 280 core1 { 281 cpu = <&CPU17>; 282 }; 283 }; 284 cluster9 { 285 core0 { 286 cpu = <&CPU18>; 287 }; 288 core1 { 289 cpu = <&CPU19>; 290 }; 291 }; 292 cluster10 { 293 core0 { 294 cpu = <&CPU20>; 295 }; 296 core1 { 297 cpu = <&CPU21>; 298 }; 299 }; 300 cluster11 { 301 core0 { 302 cpu = <&CPU22>; 303 }; 304 core1 { 305 cpu = <&CPU23>; 306 }; 307 }; 308 }; 309 }; 310 311 idle-states { 312 entry-method = "psci"; 313 314 CPU_SLEEP_0: cpu-sleep-0 { 315 compatible = "arm,idle-state"; 316 arm,psci-suspend-param = <0x0010000>; 317 entry-latency-us = <300>; 318 exit-latency-us = <1200>; 319 min-residency-us = <2000>; 320 local-timer-stop; 321 }; 322 323 CLUSTER_SLEEP_0: cluster-sleep-0 { 324 compatible = "arm,idle-state"; 325 arm,psci-suspend-param = <0x1010000>; 326 entry-latency-us = <400>; 327 exit-latency-us = <1200>; 328 min-residency-us = <2500>; 329 local-timer-stop; 330 }; 331 }; 332 333 gic: interrupt-controller@30000000 { 334 compatible = "arm,gic-v3"; 335 reg = <0x0 0x30000000 0x0 0x10000>, // GICD 336 <0x0 0x30400000 0x0 0x300000>, // GICR 337 <0x0 0x2c000000 0x0 0x2000>, // GICC 338 <0x0 0x2c010000 0x0 0x1000>, // GICH 339 <0x0 0x2c020000 0x0 0x10000>; // GICV 340 #interrupt-cells = <3>; 341 #address-cells = <2>; 342 #size-cells = <2>; 343 ranges; 344 interrupt-controller; 345 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 346 347 its: msi-controller@30020000 { 348 compatible = "arm,gic-v3-its"; 349 reg = <0x0 0x30020000 0x0 0x20000>; 350 #msi-cells = <1>; 351 msi-controller; 352 socionext,synquacer-pre-its = <0x58000000 0x200000>; 353 }; 354 }; 355 356 timer { 357 compatible = "arm,armv8-timer"; 358 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure 359 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure 360 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual 361 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP 362 }; 363 364 timer@2a810000 { 365 compatible = "arm,armv7-timer-mem"; 366 reg = <0x0 0x2a810000 0x0 0x10000>; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges = <0x0 0x0 0x2a810000 0x30000>; 370 frame@20000 { 371 frame-number = <0>; 372 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 373 reg = <0x20000 0x10000>; 374 }; 375 }; 376 377 pmu { 378 compatible = "arm,cortex-a53-pmu"; 379 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 380 }; 381 382 psci { 383 compatible = "arm,psci-1.0"; 384 method = "smc"; 385 }; 386 387 clk_uart: refclk62500khz { 388 compatible = "fixed-clock"; 389 #clock-cells = <0>; 390 clock-frequency = <62500000>; 391 clock-output-names = "uartclk"; 392 }; 393 394 clk_apb: refclk100mhz { 395 compatible = "fixed-clock"; 396 #clock-cells = <0>; 397 clock-frequency = <100000000>; 398 clock-output-names = "apb_pclk"; 399 }; 400 401 soc_uart0: serial@2a400000 { 402 compatible = "arm,pl011", "arm,primecell"; 403 reg = <0x0 0x2a400000 0x0 0x1000>; 404 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&clk_uart>, <&clk_apb>; 406 clock-names = "uartclk", "apb_pclk"; 407 }; 408 409 fuart: serial@51040000 { 410 compatible = "snps,dw-apb-uart"; 411 reg = <0x0 0x51040000 0x0 0x1000>; 412 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clk_uart>, <&clk_apb>; 414 clock-names = "baudclk", "apb_pclk"; 415 reg-io-width = <4>; 416 reg-shift = <2>; 417 }; 418 419 clk_netsec: refclk250mhz { 420 compatible = "fixed-clock"; 421 clock-frequency = <250000000>; 422 #clock-cells = <0>; 423 }; 424 425 netsec: ethernet@522d0000 { 426 compatible = "socionext,synquacer-netsec"; 427 reg = <0 0x522d0000 0x0 0x10000>, 428 <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; 429 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clk_netsec>; 431 clock-names = "phy_ref_clk"; 432 max-speed = <1000>; 433 max-frame-size = <9000>; 434 phy-handle = <&phy_netsec>; 435 dma-coherent; 436 437 mdio_netsec: mdio { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 }; 442 443 smmu: iommu@582c0000 { 444 compatible = "arm,mmu-500", "arm,smmu-v2"; 445 reg = <0x0 0x582c0000 0x0 0x10000>; 446 #global-interrupts = <1>; 447 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 450 #iommu-cells = <1>; 451 status = "disabled"; 452 }; 453 454 pcie0: pcie@60000000 { 455 compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; 456 device_type = "pci"; 457 reg = <0x0 0x60000000 0x0 0x7f00000>; 458 bus-range = <0x0 0x7e>; 459 #address-cells = <3>; 460 #size-cells = <2>; 461 ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>, 462 <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>, 463 <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>; 464 465 #interrupt-cells = <0x1>; 466 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 467 interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 468 469 msi-map = <0x000 &its 0x0 0x7f00>; 470 dma-coherent; 471 status = "disabled"; 472 }; 473 474 pcie1: pcie@70000000 { 475 compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; 476 device_type = "pci"; 477 reg = <0x0 0x70000000 0x0 0x7f00000>; 478 bus-range = <0x0 0x7e>; 479 #address-cells = <3>; 480 #size-cells = <2>; 481 ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, 482 <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, 483 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; 484 485 #interrupt-cells = <0x1>; 486 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 487 interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 488 489 msi-map = <0x0 &its 0x10000 0x7f00>; 490 dma-coherent; 491 status = "disabled"; 492 }; 493 494 gpio: gpio@51000000 { 495 compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio"; 496 reg = <0x0 0x51000000 0x0 0x100>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 clocks = <&clk_apb>; 500 }; 501 502 exiu: interrupt-controller@510c0000 { 503 compatible = "socionext,synquacer-exiu"; 504 reg = <0x0 0x510c0000 0x0 0x20>; 505 interrupt-controller; 506 interrupt-parent = <&gic>; 507 #interrupt-cells = <3>; 508 socionext,spi-base = <112>; 509 }; 510 511 clk_alw_b_0: bclk200 { 512 compatible = "fixed-clock"; 513 #clock-cells = <0>; 514 clock-frequency = <200000000>; 515 clock-output-names = "sd_bclk"; 516 }; 517 518 clk_alw_c_0: sd4clk800 { 519 compatible = "fixed-clock"; 520 #clock-cells = <0>; 521 clock-frequency = <800000000>; 522 clock-output-names = "sd_sd4clk"; 523 }; 524 525 sdhci: mmc@52300000 { 526 compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; 527 reg = <0 0x52300000 0x0 0x1000>; 528 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 530 bus-width = <8>; 531 cap-mmc-highspeed; 532 fujitsu,cmd-dat-delay-select; 533 clocks = <&clk_alw_c_0 &clk_alw_b_0>; 534 clock-names = "core", "iface"; 535 dma-coherent; 536 status = "disabled"; 537 }; 538 539 clk_alw_1_8: spi_ihclk { 540 compatible = "fixed-clock"; 541 #clock-cells = <0>; 542 clock-frequency = <125000000>; 543 clock-output-names = "iHCLK"; 544 }; 545 546 spi: spi@54810000 { 547 compatible = "socionext,synquacer-spi"; 548 reg = <0x0 0x54810000 0x0 0x1000>; 549 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clk_alw_1_8>; 553 clock-names = "iHCLK"; 554 socionext,use-rtm; 555 socionext,set-aces; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 clk_i2c: i2c_pclk { 562 compatible = "fixed-clock"; 563 #clock-cells = <0>; 564 clock-frequency = <62500000>; 565 clock-output-names = "pclk"; 566 }; 567 568 i2c: i2c@51210000 { 569 compatible = "socionext,synquacer-i2c"; 570 reg = <0x0 0x51210000 0x0 0x1000>; 571 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&clk_i2c>; 573 clock-names = "pclk"; 574 clock-frequency = <400000>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 579 tpm: tpm_tis@10000000 { 580 compatible = "socionext,synquacer-tpm-mmio"; 581 reg = <0x0 0x10000000 0x0 0x5000>; 582 status = "disabled"; 583 }; 584 585 firmware { 586 optee { 587 compatible = "linaro,optee-tz"; 588 method = "smc"; 589 status = "disabled"; 590 }; 591 }; 592}; 593 594#include "synquacer-sc2a11-caches.dtsi" 595