1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * clock.h 4 * 5 * clock header 6 * 7 * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ 8 */ 9 10 #ifndef _CLOCKS_H_ 11 #define _CLOCKS_H_ 12 13 #include <asm/arch/clocks_am33xx.h> 14 #include <asm/arch/hardware.h> 15 16 #if defined(CONFIG_TI816X) 17 #include <asm/arch/clock_ti81xx.h> 18 #endif 19 20 #define LDELAY 1000000 21 22 /*CM_<clock_domain>__CLKCTRL */ 23 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 24 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 25 26 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 27 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 28 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 29 30 /* CM_<clock_domain>_<module>_CLKCTRL */ 31 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 32 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 33 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 34 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 35 36 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 37 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 38 39 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 40 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 41 #define MODULE_CLKCTRL_IDLEST_IDLE 2 42 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 43 44 /* CM_CLKMODE_DPLL */ 45 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 46 #define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) 47 #define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13) 48 #define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 49 #define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15) 50 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 51 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 52 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 53 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 54 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 55 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 56 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 57 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 58 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 59 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 60 #define CM_CLKMODE_DPLL_EN_SHIFT 0 61 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 62 63 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 64 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 65 66 #define DPLL_EN_STOP 1 67 #define DPLL_EN_MN_BYPASS 4 68 #define DPLL_EN_LOW_POWER_BYPASS 5 69 #define DPLL_EN_FAST_RELOCK_BYPASS 6 70 #define DPLL_EN_LOCK 7 71 72 /* CM_IDLEST_DPLL fields */ 73 #define ST_DPLL_CLK_MASK 1 74 75 /* CM_CLKSEL_DPLL */ 76 #define CM_CLKSEL_DPLL_M_SHIFT 8 77 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 78 #define CM_CLKSEL_DPLL_N_SHIFT 0 79 #define CM_CLKSEL_DPLL_N_MASK 0x7F 80 81 /* CM_SSC_DELTAM_DPLL */ 82 #define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0 83 #define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0) 84 #define CM_SSC_DELTAM_DPLL_INT_SHIFT 18 85 #define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18) 86 87 /* CM_SSC_MODFREQ_DPLL */ 88 #define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0 89 #define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0) 90 #define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7 91 #define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8) 92 93 struct dpll_params { 94 u32 m; 95 u32 n; 96 s8 m2; 97 s8 m3; 98 s8 m4; 99 s8 m5; 100 s8 m6; 101 }; 102 103 struct dpll_regs { 104 u32 cm_clkmode_dpll; 105 u32 cm_idlest_dpll; 106 u32 cm_autoidle_dpll; 107 u32 cm_clksel_dpll; 108 u32 cm_div_m2_dpll; 109 u32 cm_div_m3_dpll; 110 u32 cm_div_m4_dpll; 111 u32 cm_div_m5_dpll; 112 u32 cm_div_m6_dpll; 113 }; 114 115 extern const struct dpll_regs dpll_mpu_regs; 116 extern const struct dpll_regs dpll_core_regs; 117 extern const struct dpll_regs dpll_per_regs; 118 extern const struct dpll_regs dpll_ddr_regs; 119 extern const struct dpll_regs dpll_disp_regs; 120 extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; 121 extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; 122 extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; 123 extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; 124 extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; 125 extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ]; 126 127 extern struct cm_wkuppll *const cmwkup; 128 129 const struct dpll_params *get_dpll_mpu_params(void); 130 const struct dpll_params *get_dpll_core_params(void); 131 const struct dpll_params *get_dpll_per_params(void); 132 const struct dpll_params *get_dpll_ddr_params(void); 133 void scale_vcores(void); 134 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); 135 void prcm_init(void); 136 void enable_basic_clocks(void); 137 138 void rtc_only_update_board_type(u32 btype); 139 u32 rtc_only_get_board_type(void); 140 void rtc_only_prcm_init(void); 141 void rtc_only_enable_basic_clocks(void); 142 143 void do_enable_clocks(u32 *const *, u32 *const *, u8); 144 void do_disable_clocks(u32 *const *, u32 *const *, u8); 145 146 void set_mpu_spreadspectrum(int permille); 147 #endif 148