1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Common definitions for LPC32XX board configurations 4 * 5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 6 */ 7 8 #ifndef _LPC32XX_CONFIG_H 9 #define _LPC32XX_CONFIG_H 10 11 12 /* Basic CPU architecture */ 13 14 #if !defined(CFG_SYS_NS16550_CLK) 15 #define CFG_SYS_NS16550_CLK 13000000 16 #endif 17 18 #define CFG_SYS_BAUDRATE_TABLE \ 19 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } 20 21 /* NAND */ 22 #if defined(CONFIG_NAND_LPC32XX_SLC) 23 #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 24 #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 25 26 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) 27 #define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 28 48, 49, 50, 51, 52, 53, 54, 55, \ 29 56, 57, 58, 59, 60, 61, 62, 63, } 30 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) 31 #define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } 32 #else 33 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" 34 #endif 35 36 #define CFG_SYS_NAND_ECCSIZE 0x100 37 #define CFG_SYS_NAND_ECCBYTES 3 38 #endif /* CONFIG_NAND_LPC32XX_SLC */ 39 40 /* NOR Flash */ 41 42 /* USB OHCI */ 43 #if defined(CONFIG_USB_OHCI_LPC32XX) 44 #define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE 45 #endif 46 47 #endif /* _LPC32XX_CONFIG_H */ 48