1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014, Freescale Semiconductor
4  */
5 
6 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
7 #define _ASM_ARMV7_LS102XA_CONFIG_
8 
9 #define OCRAM_BASE_ADDR				0x10000000
10 #define OCRAM_SIZE				0x00010000
11 #define OCRAM_BASE_S_ADDR			0x10010000
12 #define OCRAM_S_SIZE				0x00010000
13 
14 #define CFG_SYS_DCSRBAR			0x20000000
15 
16 #define CFG_SYS_DCSR_DCFG_ADDR	(CFG_SYS_DCSRBAR + 0x00220000)
17 #define SYS_FSL_DCSR_RCPM_ADDR	(CFG_SYS_DCSRBAR + 0x00222000)
18 
19 #define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
20 #define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
21 #define CFG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
22 #define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
23 #define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
24 #define CFG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
25 #define CFG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
26 #define CFG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
27 #define CFG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
28 #define CFG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
29 #define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
30 #define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
31 #define CFG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
32 #define CFG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
33 #define CFG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
34 #define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
35 #define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
36 
37 #define CFG_SYS_FSL_SEC_OFFSET		0x00700000
38 #define CFG_SYS_FSL_JR0_OFFSET		0x00710000
39 
40 #define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
41 
42 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
43 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
44 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
45 
46 #define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
47 
48 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
49 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
50 
51 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
52 
53 #define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
54 #define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
55 
56 #define CFG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
57 #define CFG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
58 #define CFG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
59 #define CFG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
60 #define CFG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
61 /*
62  * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
63  * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
64  */
65 #define CFG_SYS_PCIE1_PHYS_ADDR		(CFG_SYS_PCIE1_PHYS_BASE + \
66 						 CFG_SYS_PCIE1_VIRT_ADDR)
67 #define CFG_SYS_PCIE2_PHYS_ADDR		(CFG_SYS_PCIE2_PHYS_BASE + \
68 						 CFG_SYS_PCIE2_VIRT_ADDR)
69 
70 /* SATA */
71 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
72 #ifdef CONFIG_DDR_SPD
73 #define CFG_MAX_MEM_MAPPED			((phys_size_t)2 << 30)
74 #endif
75 
76 #define DCU_LAYER_MAX_NUM			16
77 
78 #ifdef CONFIG_ARCH_LS1021A
79 #else
80 #error SoC not defined
81 #endif
82 
83 #define FSL_IFC_COMPAT		"fsl,ifc"
84 #define FSL_QSPI_COMPAT		"fsl,ls1021a-qspi"
85 #define FSL_DSPI_COMPAT		"fsl,ls1021a-v1.0-dspi"
86 
87 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
88