1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 */ 6 7 #ifndef __ASM_ARCH_CLOCK_H 8 #define __ASM_ARCH_CLOCK_H 9 10 #include <linux/types.h> 11 12 #ifdef CONFIG_SYS_MX6_HCLK 13 #define MXC_HCLK CONFIG_SYS_MX6_HCLK 14 #else 15 #define MXC_HCLK 24000000 16 #endif 17 18 #ifdef CONFIG_SYS_MX6_CLK32 19 #define MXC_CLK32 CONFIG_SYS_MX6_CLK32 20 #else 21 #define MXC_CLK32 32768 22 #endif 23 24 struct cmd_tbl; 25 26 enum mxc_clock { 27 MXC_ARM_CLK = 0, 28 MXC_PER_CLK, 29 MXC_AHB_CLK, 30 MXC_IPG_CLK, 31 MXC_IPG_PERCLK, 32 MXC_UART_CLK, 33 MXC_CSPI_CLK, 34 MXC_AXI_CLK, 35 MXC_EMI_SLOW_CLK, 36 MXC_DDR_CLK, 37 MXC_ESDHC_CLK, 38 MXC_ESDHC2_CLK, 39 MXC_ESDHC3_CLK, 40 MXC_ESDHC4_CLK, 41 MXC_SATA_CLK, 42 MXC_NFC_CLK, 43 MXC_I2C_CLK, 44 MXC_LCDIF1_CLK, 45 MXC_LCDIF2_CLK, 46 }; 47 48 enum ldb_di_clock { 49 MXC_PLL5_CLK = 0, 50 MXC_PLL2_PFD0_CLK, 51 MXC_PLL2_PFD2_CLK, 52 MXC_MMDC_CH1_CLK, 53 MXC_PLL3_SW_CLK, 54 }; 55 56 enum enet_freq { 57 ENET_25MHZ, 58 ENET_50MHZ, 59 ENET_100MHZ, 60 ENET_125MHZ, 61 }; 62 63 u32 imx_get_uartclk(void); 64 u32 imx_get_fecclk(void); 65 unsigned int mxc_get_clock(enum mxc_clock clk); 66 void setup_gpmi_io_clk(u32 cfg); 67 void hab_caam_clock_enable(unsigned char enable); 68 void enable_ocotp_clk(unsigned char enable); 69 void enable_usboh3_clk(unsigned char enable); 70 void enable_uart_clk(unsigned char enable); 71 int enable_usdhc_clk(unsigned char enable, unsigned bus_num); 72 int enable_sata_clock(void); 73 void disable_sata_clock(void); 74 int enable_pcie_clock(void); 75 int enable_i2c_clk(unsigned char enable, unsigned i2c_num); 76 int enable_spi_clk(unsigned char enable, unsigned spi_num); 77 void enable_ipu_clock(void); 78 void disable_ipu_clock(void); 79 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); 80 void enable_enet_clk(unsigned char enable); 81 int enable_lcdif_clock(u32 base_addr, bool enable); 82 void enable_qspi_clk(int qspi_num); 83 void enable_thermal_clk(void); 84 void mxs_set_lcdclk(u32 base_addr, u32 freq); 85 void select_ldb_di_clock_source(enum ldb_di_clock clk); 86 void enable_eim_clk(unsigned char enable); 87 int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, 88 char *const argv[]); 89 #endif /* __ASM_ARCH_CLOCK_H */ 90