1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef _NPCM_OTP_H_ 4 #define _NPCM_OTP_H_ 5 6 #ifdef CONFIG_ARCH_NPCM8XX 7 enum { 8 NPCM_KEY_SA = 0, 9 NPCM_FUSE_SA = 0, 10 NPCM_NUM_OF_SA = 1 11 }; 12 #else 13 enum { 14 NPCM_KEY_SA = 0, 15 NPCM_FUSE_SA = 1, 16 NPCM_NUM_OF_SA = 2 17 }; 18 #endif 19 20 /* arrray images in flash, to program during fisrt boot (offsets in sector) */ 21 #define SA_KEYS_FLASH_IMAGE_OFFSET (0x000) 22 #define SA_FUSE_FLASH_IMAGE_OFFSET (0x400) 23 #define SA_TAG_FLASH_IMAGE_OFFSET (0x800) 24 /* F U S E I M G S */ 25 #define SA_TAG_FLASH_IMAGE_VAL {0x46, 0x55, 0x53, 0x45, 0x49, 0x4d, 0x47, 0x53} 26 #define SA_TAG_FLASH_IMAGE_SIZE (8) 27 28 #define SA_FUSE_FUSTRAP_OFFSET (0x00) 29 #define SA_FUSE_FUSTRAP_OSECBOOT_MASK (0x00800000) 30 31 struct npcm_otp_regs { 32 unsigned int fst; 33 unsigned int faddr; 34 unsigned int fdata; 35 unsigned int fcfg; 36 unsigned int fustrap_fkeyind; 37 unsigned int fctl; 38 }; 39 40 #define FST_RDY BIT(0) 41 #define FST_RDST BIT(1) 42 #define FST_RIEN BIT(2) 43 44 #ifdef CONFIG_ARCH_NPCM8XX 45 #define FADDR_BYTEADDR(addr) ((addr) << 3) 46 #define FADDR_BITPOS(pos) ((pos) << 0) 47 #define FADDR_VAL(addr, pos) (FADDR_BITPOS(pos) | FADDR_BYTEADDR(addr)) 48 #define FADDR_IN_PROG BIT(16) 49 #else 50 #define FADDR_BYTEADDR(addr) ((addr) << 0) 51 #define FADDR_BITPOS(pos) ((pos) << 10) 52 #define FADDR_VAL(addr, pos) (FADDR_BYTEADDR(addr) | FADDR_BITPOS(pos)) 53 #endif 54 55 #define FDATA_MASK (0xff) 56 57 #define FUSTRAP_O_SECBOOT BIT(23) 58 #define FCFG_FDIS BIT(31) 59 #define FKEYIND_KVAL BIT(0) 60 #define FKEYIND_KSIZE_MASK (0x00000070) 61 #define FKEYIND_KSIZE_128 (0x4 << 4) 62 #define FKEYIND_KSIZE_192 (0x5 << 4) 63 #define FKEYIND_KSIZE_256 (0x6 << 4) 64 #define FKEYIND_KIND_MASK (0x000c0000) 65 #define FKEYIND_KIND_KEY(indx) ((indx) << 18) 66 67 /* Program cycle initiation values (sequence of two adjacent writes) */ 68 #define PROGRAM_ARM 0x1 69 #define PROGRAM_INIT 0xBF79E5D0 70 71 /* Read cycle initiation value */ 72 #define READ_INIT 0x02 73 74 /* Value to clean FDATA contents */ 75 #define FDATA_CLEAN_VALUE 0x01 76 77 #ifdef CONFIG_ARCH_NPCM8XX 78 #define NPCM_OTP_ARR_BYTE_SIZE 8192 79 #else 80 #define NPCM_OTP_ARR_BYTE_SIZE 1024 81 #endif 82 83 #define MIN_PROGRAM_PULSES 4 84 #define MAX_PROGRAM_PULSES 20 85 86 int fuse_prog_image(u32 bank, uintptr_t address); 87 int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size); 88 int npcm_otp_select_key(u8 key_index); 89 bool npcm_otp_is_fuse_array_disabled(u32 arr); 90 void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size); 91 void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size); 92 93 #endif 94