1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the Allwinner A64 (sun50i) CPU 4 */ 5 6 #if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) 7 /* reserve space for BOOT0 header information */ 8 b reset 9 .space 1532 10 #elif defined(CONFIG_ARM_BOOT_HOOK_RMR) 11 /* 12 * Switch into AArch64 if needed. 13 * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source. 14 */ 15 tst x0, x0 // this is "b #0x84" in ARM 16 b reset 17 .space 0x7c 18 19 .word 0xe28f0070 // add r0, pc, #112 // @(fel_stash - .) 20 .word 0xe59f106c // ldr r1, [pc, #108] // fel_stash - . 21 .word 0xe0800001 // add r0, r0, r1 22 .word 0xe580d000 // str sp, [r0] 23 .word 0xe580e004 // str lr, [r0, #4] 24 .word 0xe10fe000 // mrs lr, CPSR 25 .word 0xe580e008 // str lr, [r0, #8] 26 .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} 27 .word 0xe580e00c // str lr, [r0, #12] 28 .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} 29 .word 0xe580e010 // str lr, [r0, #16] 30 31 .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS 32 .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE 33 .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG 34 .word 0xe21000ff // ands r0, r0, #255 ; 0xff 35 .word 0x159f102c // ldrne r1, [pc, #44] ; RVBAR_ALTERNATIVE 36 .word 0xe59f002c // ldr r0, [pc, #44] ; CONFIG_*TEXT_BASE 37 .word 0xe5810000 // str r0, [r1] 38 .word 0xf57ff04f // dsb sy 39 .word 0xf57ff06f // isb sy 40 .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR 41 .word 0xe3800003 // orr r0, r0, #3 42 .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR 43 .word 0xf57ff06f // isb sy 44 .word 0xe320f003 // wfi 45 .word 0xeafffffd // b @wfi 46 47 .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr 48 .word SUNXI_SRAMC_BASE 49 .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant 50 #ifdef CONFIG_SPL_BUILD 51 .word CONFIG_SPL_TEXT_BASE 52 #else 53 .word CONFIG_TEXT_BASE 54 #endif 55 .word fel_stash - . 56 #else 57 /* normal execution */ 58 b reset 59 #endif 60