1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * NVIDIA Tegra I2C controller
4 *
5 * Copyright 2010-2011 NVIDIA Corporation
6 */
7
8 #ifndef _TEGRA_I2C_H_
9 #define _TEGRA_I2C_H_
10
11 #include <asm/io.h>
12 #include <asm/types.h>
13
14 struct udevice;
15
16 enum {
17 I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
18 I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
19 };
20
21 enum i2c_transaction_flags {
22 I2C_IS_WRITE = 0x1, /* for I2C write operation */
23 I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
24 I2C_USE_REPEATED_START = 0x4, /* for repeat start */
25 I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
26 I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
27 I2C_NO_STOP = 0x20,
28 };
29
30 /* Contians the I2C transaction details */
31 struct i2c_trans_info {
32 /* flags to indicate the transaction details */
33 enum i2c_transaction_flags flags;
34 u32 address; /* I2C slave device address */
35 u32 num_bytes; /* number of bytes to be transferred */
36 /*
37 * Send/receive buffer. For the I2C send operation this buffer should
38 * be filled with the data to be sent to the slave device. For the I2C
39 * receive operation this buffer is filled with the data received from
40 * the slave device.
41 */
42 u8 *buf;
43 int is_10bit_address;
44 };
45
46 struct i2c_control {
47 u32 tx_fifo;
48 u32 rx_fifo;
49 u32 packet_status;
50 u32 fifo_control;
51 u32 fifo_status;
52 u32 int_mask;
53 u32 int_status;
54 };
55
56 struct dvc_ctlr {
57 u32 ctrl1; /* 00: DVC_CTRL_REG1 */
58 u32 ctrl2; /* 04: DVC_CTRL_REG2 */
59 u32 ctrl3; /* 08: DVC_CTRL_REG3 */
60 u32 status; /* 0C: DVC_STATUS_REG */
61 u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
62 u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
63 u32 reserved_0[2]; /* 18: */
64 u32 req; /* 20: DVC_REQ_REGISTER */
65 u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
66 u32 reserved_1[6]; /* 28: */
67 u32 cnfg; /* 40: DVC_I2C_CNFG */
68 u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
69 u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
70 u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
71 u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
72 u32 reserved_2[2]; /* 54: */
73 u32 i2c_status; /* 5C: DVC_I2C_STATUS */
74 struct i2c_control control; /* 60 ~ 78 */
75 };
76
77 struct i2c_ctlr {
78 u32 cnfg; /* 00: I2C_I2C_CNFG */
79 u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
80 u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
81 u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
82 u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
83 u32 reserved_0[2]; /* 14: */
84 u32 status; /* 1C: I2C_I2C_STATUS */
85 u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
86 u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
87 u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
88 u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
89 u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
90 u32 reserved_1[2]; /* 34: */
91 u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
92 u32 reserved_2[4]; /* 40: */
93 struct i2c_control control; /* 50 ~ 68 */
94 u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
95 };
96
97 /* bit fields definitions for IO Packet Header 1 format */
98 #define PKT_HDR1_PROTOCOL_SHIFT 4
99 #define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
100 #define PKT_HDR1_CTLR_ID_SHIFT 12
101 #define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
102 #define PKT_HDR1_PKT_ID_SHIFT 16
103 #define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
104 #define PROTOCOL_TYPE_I2C 1
105
106 /* bit fields definitions for IO Packet Header 2 format */
107 #define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
108 #define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
109
110 /* bit fields definitions for IO Packet Header 3 format */
111 #define PKT_HDR3_READ_MODE_SHIFT 19
112 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
113 #define PKT_HDR3_REPEAT_START_SHIFT 16
114 #define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT)
115 #define PKT_HDR3_SLAVE_ADDR_SHIFT 0
116 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
117
118 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
119 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
120 (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
121
122 /* I2C_CNFG */
123 #define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
124 #define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
125 #define I2C_CNFG_PACKET_MODE_SHIFT 10
126 #define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
127
128 /* I2C_SL_CNFG */
129 #define I2C_SL_CNFG_NEWSL_SHIFT 2
130 #define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
131
132 /* I2C_FIFO_STATUS */
133 #define TX_FIFO_FULL_CNT_SHIFT 0
134 #define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
135 #define TX_FIFO_EMPTY_CNT_SHIFT 4
136 #define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
137
138 /* I2C_INTERRUPT_STATUS */
139 #define I2C_INT_XFER_COMPLETE_SHIFT 7
140 #define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
141 #define I2C_INT_NO_ACK_SHIFT 3
142 #define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
143 #define I2C_INT_ARBITRATION_LOST_SHIFT 2
144 #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
145
146 /* I2C_CLK_DIVISOR_REGISTER */
147 #define CLK_DIV_STD_FAST_MODE 0x19
148 #define CLK_DIV_HS_MODE 1
149 #define CLK_MULT_STD_FAST_MODE 8
150
151 /**
152 * Returns the bus number of the DVC controller
153 *
154 * Return: number of bus, or -1 if there is no DVC active
155 */
156 int tegra_i2c_get_dvc_bus(struct udevice **busp);
157
158 /* Pre-dm section used for initial setup of PMIC */
159 #define I2C_SEND_2_BYTES 0x0A02
160
tegra_i2c_ll_write(uint addr,uint data)161 static inline void tegra_i2c_ll_write(uint addr, uint data)
162 {
163 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
164
165 writel(addr, ®->cmd_addr0);
166 writel(0x2, ®->cnfg);
167
168 writel(data, ®->cmd_data1);
169 writel(I2C_SEND_2_BYTES, ®->cnfg);
170 }
171
172 void pmic_enable_cpu_vdd(void);
173
174 #endif /* _TEGRA_I2C_H_ */
175