1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 */
6
7 #ifndef _ASM_ARMV8_MMU_H_
8 #define _ASM_ARMV8_MMU_H_
9
10 #include <hang.h>
11 #include <linux/const.h>
12
13 /*
14 * block/section address mask and size definitions.
15 */
16
17 /* PAGE_SHIFT determines the page size */
18 #undef PAGE_SIZE
19 #define PAGE_SHIFT 12
20 #define PAGE_SIZE (1 << PAGE_SHIFT)
21 #define PAGE_MASK (~(PAGE_SIZE - 1))
22
23 /***************************************************************/
24
25 /*
26 * Memory types
27 */
28 #define MT_DEVICE_NGNRNE 0
29 #define MT_DEVICE_NGNRE 1
30 #define MT_DEVICE_GRE 2
31 #define MT_NORMAL_NC 3
32 #define MT_NORMAL 4
33
34 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
35 (0x04 << (MT_DEVICE_NGNRE * 8)) | \
36 (0x0c << (MT_DEVICE_GRE * 8)) | \
37 (0x44 << (MT_NORMAL_NC * 8)) | \
38 (UL(0xff) << (MT_NORMAL * 8)))
39
40 /*
41 * Hardware page table definitions.
42 *
43 */
44
45 #define PTE_TYPE_MASK (3 << 0)
46 #define PTE_TYPE_FAULT (0 << 0)
47 #define PTE_TYPE_TABLE (3 << 0)
48 #define PTE_TYPE_PAGE (3 << 0)
49 #define PTE_TYPE_BLOCK (1 << 0)
50 #define PTE_TYPE_VALID (1 << 0)
51
52 #define PTE_RDONLY BIT(7)
53 #define PTE_DBM BIT(51)
54
55 #define PTE_TABLE_PXN BIT(59)
56 #define PTE_TABLE_XN BIT(60)
57 #define PTE_TABLE_AP BIT(61)
58 #define PTE_TABLE_NS BIT(63)
59
60 /*
61 * Block
62 */
63 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
64 #define PTE_BLOCK_NS (1 << 5)
65 #define PTE_BLOCK_NON_SHARE (0 << 8)
66 #define PTE_BLOCK_OUTER_SHARE (2 << 8)
67 #define PTE_BLOCK_INNER_SHARE (3 << 8)
68 #define PTE_BLOCK_AF (1 << 10)
69 #define PTE_BLOCK_NG (1 << 11)
70 #define PTE_BLOCK_PXN (UL(1) << 53)
71 #define PTE_BLOCK_UXN (UL(1) << 54)
72
73 /*
74 * AttrIndx[2:0]
75 */
76 #define PMD_ATTRINDX(t) ((t) << 2)
77 #define PMD_ATTRINDX_MASK (7 << 2)
78 #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
79 PTE_BLOCK_UXN | \
80 PMD_ATTRINDX_MASK | \
81 PTE_TYPE_VALID)
82
83 /*
84 * TCR flags.
85 */
86 #define TCR_T0SZ(x) ((64 - (x)) << 0)
87 #define TCR_IRGN_NC (0 << 8)
88 #define TCR_IRGN_WBWA (1 << 8)
89 #define TCR_IRGN_WT (2 << 8)
90 #define TCR_IRGN_WBNWA (3 << 8)
91 #define TCR_IRGN_MASK (3 << 8)
92 #define TCR_ORGN_NC (0 << 10)
93 #define TCR_ORGN_WBWA (1 << 10)
94 #define TCR_ORGN_WT (2 << 10)
95 #define TCR_ORGN_WBNWA (3 << 10)
96 #define TCR_ORGN_MASK (3 << 10)
97 #define TCR_SHARED_NON (0 << 12)
98 #define TCR_SHARED_OUTER (2 << 12)
99 #define TCR_SHARED_INNER (3 << 12)
100 #define TCR_TG0_4K (0 << 14)
101 #define TCR_TG0_64K (1 << 14)
102 #define TCR_TG0_16K (2 << 14)
103 #define TCR_EPD1_DISABLE (1 << 23)
104
105 #define TCR_EL1_HA BIT(39)
106 #define TCR_EL1_HD BIT(40)
107
108 #define TCR_EL2_HA BIT(21)
109 #define TCR_EL2_HD BIT(22)
110
111 #define TCR_EL3_HA BIT(21)
112 #define TCR_EL3_HD BIT(22)
113
114 #define TCR_EL1_RSVD (1U << 31)
115 #define TCR_EL2_RSVD (1U << 31 | 1 << 23)
116 #define TCR_EL3_RSVD (1U << 31 | 1 << 23)
117
118 #define HCR_EL2_E2H_BIT 34
119
120 #ifndef __ASSEMBLY__
set_ttbr_tcr_mair(int el,u64 table,u64 tcr,u64 attr)121 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
122 {
123 asm volatile("dsb sy");
124 if (el == 1) {
125 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
126 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
127 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
128 } else if (el == 2) {
129 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
130 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
131 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
132 } else if (el == 3) {
133 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
134 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
135 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
136 } else {
137 hang();
138 }
139 asm volatile("isb");
140 }
141
142 struct mm_region {
143 u64 virt;
144 u64 phys;
145 u64 size;
146 u64 attrs;
147 };
148
149 extern struct mm_region *mem_map;
150 void setup_pgtables(void);
151 u64 get_tcr(u64 *pips, u64 *pva_bits);
152 #endif
153
154 #endif /* _ASM_ARMV8_MMU_H_ */
155