1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2002-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #ifndef __ASM_GBL_DATA_H 8 #define __ASM_GBL_DATA_H 9 10 #ifndef __ASSEMBLY__ 11 12 #include <config.h> 13 14 #include <asm/types.h> 15 #include <linux/types.h> 16 17 /* Architecture-specific global data */ 18 struct arch_global_data { 19 #if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX) 20 u32 sdhc_clk; 21 #endif 22 23 #if defined(CONFIG_FSL_ESDHC) 24 u32 sdhc_per_clk; 25 #endif 26 27 #if defined(CONFIG_U_QE) 28 u32 qe_clk; 29 u32 brg_clk; 30 uint mp_alloc_base; 31 uint mp_alloc_top; 32 #endif /* CONFIG_U_QE */ 33 34 #ifdef CONFIG_AT91FAMILY 35 /* "static data" needed by at91's clock.c */ 36 unsigned long cpu_clk_rate_hz; 37 unsigned long main_clk_rate_hz; 38 unsigned long mck_rate_hz; 39 unsigned long plla_rate_hz; 40 unsigned long pllb_rate_hz; 41 unsigned long at91_pllb_usb_init; 42 #endif 43 /* "static data" needed by most of timer.c on ARM platforms */ 44 unsigned long timer_rate_hz; 45 unsigned int tbu; 46 unsigned int tbl; 47 unsigned long lastinc; 48 unsigned long long timer_reset_value; 49 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) 50 unsigned long tlb_addr; 51 unsigned long tlb_size; 52 #if defined(CONFIG_ARM64) 53 unsigned long tlb_fillptr; 54 unsigned long tlb_emerg; 55 unsigned int first_block_level; 56 bool has_hafdbs; 57 #endif 58 #endif 59 #ifdef CFG_SYS_MEM_RESERVE_SECURE 60 #define MEM_RESERVE_SECURE_SECURED 0x1 61 #define MEM_RESERVE_SECURE_MAINTAINED 0x2 62 #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) 63 /* 64 * Secure memory addr 65 * This variable needs maintenance if the RAM base is not zero, 66 * or if RAM splits into non-consecutive banks. It also has a 67 * flag indicating the secure memory is marked as secure by MMU. 68 * Flags used: 0x1 secured 69 * 0x2 maintained 70 */ 71 phys_addr_t secure_ram; 72 unsigned long tlb_allocated; 73 #endif 74 #ifdef CONFIG_RESV_RAM 75 /* 76 * Reserved RAM for memory resident, eg. Management Complex (MC) 77 * driver which continues to run after U-Boot exits. 78 */ 79 phys_addr_t resv_ram; 80 #endif 81 82 #ifdef CONFIG_ARCH_OMAP2PLUS 83 u32 omap_boot_device; 84 u32 omap_boot_mode; 85 u8 omap_ch_flags; 86 #endif 87 #if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) 88 unsigned long mem2_clk; 89 #endif 90 91 #ifdef CONFIG_ARCH_IMX8 92 struct udevice *scu_dev; 93 #endif 94 95 #ifdef CONFIG_IMX_SENTINEL 96 struct udevice *s400_dev; 97 u32 soc_rev; 98 u32 lifecycle; 99 u32 uid[4]; 100 #endif 101 102 #ifdef CONFIG_ARCH_IMX8ULP 103 bool m33_handshake_done; 104 #endif 105 }; 106 107 #include <asm-generic/global_data.h> 108 109 #if defined(__clang__) || defined(LTO_ENABLE) 110 111 #define DECLARE_GLOBAL_DATA_PTR 112 #define gd get_gd() 113 get_gd(void)114static inline gd_t *get_gd(void) 115 { 116 gd_t *gd_ptr; 117 118 #ifdef CONFIG_ARM64 119 __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr)); 120 #else 121 __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr)); 122 #endif 123 124 return gd_ptr; 125 } 126 127 #else 128 129 #ifdef CONFIG_ARM64 130 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") 131 #else 132 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") 133 #endif 134 #endif 135 set_gd(volatile gd_t * gd_ptr)136static inline void set_gd(volatile gd_t *gd_ptr) 137 { 138 #ifdef CONFIG_ARM64 139 __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr)); 140 #elif __ARM_ARCH >= 7 141 __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr)); 142 #else 143 __asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr)); 144 #endif 145 } 146 147 #endif /* __ASSEMBLY__ */ 148 149 #endif /* __ASM_GBL_DATA_H */ 150