1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
3
4 #include <linux/compiler.h>
5 #include <asm/barriers.h>
6
7 #ifdef CONFIG_ARM64
8
9 /*
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
11 */
12 #define CR_M (1 << 0) /* MMU enable */
13 #define CR_A (1 << 1) /* Alignment abort enable */
14 #define CR_C (1 << 2) /* Dcache enable */
15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16 #define CR_I (1 << 12) /* Icache enable */
17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
18 #define CR_EE (1 << 25) /* Exception (Big) Endian */
19
20 #define ES_TO_AARCH64 1
21 #define ES_TO_AARCH32 0
22
23 /*
24 * SCR_EL3 bits definitions
25 */
26 #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
27 #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
28 #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
29 #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
30 #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
31 #define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
32 #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
33
34 /*
35 * SPSR_EL3/SPSR_EL2 bits definitions
36 */
37 #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
38 #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
39 #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
40 #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
41 #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
42 #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
43 #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
44 #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
45 #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
46 #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
47 #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
48 #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
49 #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
50
51 /*
52 * CPTR_EL2 bits definitions
53 */
54 #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
55
56 /*
57 * SCTLR_EL2 bits definitions
58 */
59 #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
60 1 << 11 | 3 << 4) /* Reserved, RES1 */
61 #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
62 #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
63 #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
64 #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
65 #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
66 #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
67 #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
68
69 /*
70 * CNTHCTL_EL2 bits definitions
71 */
72 #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
73 #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
74
75 /*
76 * HCR_EL2 bits definitions
77 */
78 #define HCR_EL2_API (1 << 41) /* Trap pointer authentication
79 instructions */
80 #define HCR_EL2_APK (1 << 40) /* Trap pointer authentication
81 key access */
82 #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
83 #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
84 #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
85 #define HCR_EL2_AMO_EL2 (1 << 5) /* Route SErrors to EL2 */
86
87 /*
88 * ID_AA64ISAR1_EL1 bits definitions
89 */
90 #define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic
91 code auth algorithm */
92 #define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth
93 algorithm */
94 #define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address
95 auth algorithm */
96 #define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */
97
98 /*
99 * ID_AA64PFR0_EL1 bits definitions
100 */
101 #define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */
102 #define ID_AA64PFR0_EL1_EL2 (0xF << 8) /* EL2 implemented */
103
104 /*
105 * CPACR_EL1 bits definitions
106 */
107 #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
108
109 /*
110 * SCTLR_EL1 bits definitions
111 */
112 #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
113 1 << 11) /* Reserved, RES1 */
114 #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
115 #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
116 #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
117 #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
118 #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
119 #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
120 #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
121 #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
122 #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
123 #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
124 #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
125 #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
126 #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
127 #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
128 #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
129 #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
130 #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
131
132 #ifndef __ASSEMBLY__
133
134 struct pt_regs;
135
136 u64 get_page_table_size(void);
137 #define PGTABLE_SIZE get_page_table_size()
138
139 /* 2MB granularity */
140 #define MMU_SECTION_SHIFT 21
141 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
142
143 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
144 enum dcache_option {
145 DCACHE_OFF = 0 << 2,
146 DCACHE_WRITETHROUGH = 3 << 2,
147 DCACHE_WRITEBACK = 4 << 2,
148 DCACHE_WRITEALLOC = 4 << 2,
149 };
150
151 #define wfi() \
152 ({asm volatile( \
153 "wfi" : : : "memory"); \
154 })
155
current_el(void)156 static inline unsigned int current_el(void)
157 {
158 unsigned long el;
159
160 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
161 return 3 & (el >> 2);
162 }
163
get_sctlr(void)164 static inline unsigned int get_sctlr(void)
165 {
166 unsigned int el;
167 unsigned long val;
168
169 el = current_el();
170 if (el == 1)
171 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
172 else if (el == 2)
173 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
174 else
175 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
176
177 return val;
178 }
179
set_sctlr(unsigned long val)180 static inline void set_sctlr(unsigned long val)
181 {
182 unsigned int el;
183
184 el = current_el();
185 if (el == 1)
186 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
187 else if (el == 2)
188 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
189 else
190 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
191
192 asm volatile("isb");
193 }
194
read_mpidr(void)195 static inline unsigned long read_mpidr(void)
196 {
197 unsigned long val;
198
199 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
200
201 return val;
202 }
203
204 #define BSP_COREID 0
205
206 void __asm_flush_dcache_all(void);
207 void __asm_invalidate_dcache_all(void);
208 void __asm_flush_dcache_range(u64 start, u64 end);
209
210 /**
211 * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
212 *
213 * This performance an invalidate from @start to @end - 1. Both addresses
214 * should be cache-aligned, otherwise this function will align the start
215 * address and may continue past the end address.
216 *
217 * Data in the address range is evicted from the cache and is not written back
218 * to memory.
219 *
220 * @start: Start address to invalidate
221 * @end: End address to invalidate up to (exclusive)
222 */
223 void __asm_invalidate_dcache_range(u64 start, u64 end);
224 void __asm_invalidate_tlb_all(void);
225 void __asm_invalidate_icache_all(void);
226 int __asm_invalidate_l3_dcache(void);
227 int __asm_flush_l3_dcache(void);
228 int __asm_invalidate_l3_icache(void);
229 void __asm_switch_ttbr(u64 new_ttbr);
230
231 /*
232 * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
233 *
234 * @args: For loading 64-bit OS, fdt address.
235 * For loading 32-bit OS, zero.
236 * @mach_nr: For loading 64-bit OS, zero.
237 * For loading 32-bit OS, machine nr
238 * @fdt_addr: For loading 64-bit OS, zero.
239 * For loading 32-bit OS, fdt address.
240 * @arg4: Input argument.
241 * @entry_point: kernel entry point
242 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
243 */
244 void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
245 u64 arg4, u64 entry_point, u64 es_flag);
246 /*
247 * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
248 *
249 * @args: For loading 64-bit OS, fdt address.
250 * For loading 32-bit OS, zero.
251 * @mach_nr: For loading 64-bit OS, zero.
252 * For loading 32-bit OS, machine nr
253 * @fdt_addr: For loading 64-bit OS, zero.
254 * For loading 32-bit OS, fdt address.
255 * @arg4: Input argument.
256 * @entry_point: kernel entry point
257 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
258 */
259 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
260 u64 arg4, u64 entry_point, u64 es_flag);
261 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
262 u64 arg4, u64 entry_point);
263 void gic_init(void);
264 void gic_send_sgi(unsigned long sgino);
265 void wait_for_wakeup(void);
266 void protect_secure_region(void);
267 void smp_kick_all_cpus(void);
268
269 void flush_l3_cache(void);
270 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
271
272 /*
273 * smc_call() - issue a secure monitor call
274 *
275 * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
276 * DEN0028A
277 *
278 * @args: input and output arguments
279 */
280 void smc_call(struct pt_regs *args);
281
282 void __noreturn psci_system_reset(void);
283 void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
284 void __noreturn psci_system_off(void);
285
286 #ifdef CONFIG_ARMV8_PSCI
287 extern char __secure_start[];
288 extern char __secure_end[];
289 extern char __secure_stack_start[];
290 extern char __secure_stack_end[];
291
292 void armv8_setup_psci(void);
293 void psci_setup_vectors(void);
294 void psci_arch_init(void);
295 #endif
296
297 #endif /* __ASSEMBLY__ */
298
299 #else /* CONFIG_ARM64 */
300
301 #ifdef __KERNEL__
302
303 #define CPU_ARCH_UNKNOWN 0
304 #define CPU_ARCH_ARMv3 1
305 #define CPU_ARCH_ARMv4 2
306 #define CPU_ARCH_ARMv4T 3
307 #define CPU_ARCH_ARMv5 4
308 #define CPU_ARCH_ARMv5T 5
309 #define CPU_ARCH_ARMv5TE 6
310 #define CPU_ARCH_ARMv5TEJ 7
311 #define CPU_ARCH_ARMv6 8
312 #define CPU_ARCH_ARMv7 9
313
314 /*
315 * CR1 bits (CP#15 CR1)
316 */
317 #define CR_M (1 << 0) /* MMU enable */
318 #define CR_A (1 << 1) /* Alignment abort enable */
319 #define CR_C (1 << 2) /* Dcache enable */
320 #define CR_W (1 << 3) /* Write buffer enable */
321 #define CR_P (1 << 4) /* 32-bit exception handler */
322 #define CR_D (1 << 5) /* 32-bit data address range */
323 #define CR_L (1 << 6) /* Implementation defined */
324 #define CR_B (1 << 7) /* Big endian */
325 #define CR_S (1 << 8) /* System MMU protection */
326 #define CR_R (1 << 9) /* ROM MMU protection */
327 #define CR_F (1 << 10) /* Implementation defined */
328 #define CR_Z (1 << 11) /* Implementation defined */
329 #define CR_I (1 << 12) /* Icache enable */
330 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
331 #define CR_RR (1 << 14) /* Round Robin cache replacement */
332 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
333 #define CR_DT (1 << 16)
334 #define CR_IT (1 << 18)
335 #define CR_ST (1 << 19)
336 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
337 #define CR_U (1 << 22) /* Unaligned access operation */
338 #define CR_XP (1 << 23) /* Extended page tables */
339 #define CR_VE (1 << 24) /* Vectored interrupts */
340 #define CR_EE (1 << 25) /* Exception (Big) Endian */
341 #define CR_TRE (1 << 28) /* TEX remap enable */
342 #define CR_AFE (1 << 29) /* Access flag enable */
343 #define CR_TE (1 << 30) /* Thumb exception enable */
344
345 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
346 #define PGTABLE_SIZE (4096 * 5)
347 #elif !defined(PGTABLE_SIZE)
348 #define PGTABLE_SIZE (4096 * 4)
349 #endif
350
351 /*
352 * This is used to ensure the compiler did actually allocate the register we
353 * asked it for some inline assembly sequences. Apparently we can't trust
354 * the compiler from one version to another so a bit of paranoia won't hurt.
355 * This string is meant to be concatenated with the inline asm string and
356 * will cause compilation to stop on mismatch.
357 * (for details, see gcc PR 15089)
358 */
359 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
360
361 #ifndef __ASSEMBLY__
362
363 #ifdef CONFIG_ARMV7_LPAE
364 void switch_to_hypervisor_ret(void);
365 #endif
366
367 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
368
369 #ifdef __ARM_ARCH_7A__
370 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
371 #else
372 #define wfi()
373 #endif
374
get_cpsr(void)375 static inline unsigned long get_cpsr(void)
376 {
377 unsigned long cpsr;
378
379 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
380 return cpsr;
381 }
382
is_hyp(void)383 static inline int is_hyp(void)
384 {
385 #ifdef CONFIG_ARMV7_LPAE
386 /* HYP mode requires LPAE ... */
387 return ((get_cpsr() & 0x1f) == 0x1a);
388 #else
389 /* ... so without LPAE support we can optimize all hyp code away */
390 return 0;
391 #endif
392 }
393
get_cr(void)394 static inline unsigned int get_cr(void)
395 {
396 unsigned int val;
397
398 if (is_hyp())
399 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
400 :
401 : "cc");
402 else
403 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
404 :
405 : "cc");
406 return val;
407 }
408
set_cr(unsigned int val)409 static inline void set_cr(unsigned int val)
410 {
411 if (is_hyp())
412 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
413 : "r" (val)
414 : "cc");
415 else
416 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
417 : "r" (val)
418 : "cc");
419 isb();
420 }
421
422 #ifdef CONFIG_ARMV7_LPAE
423 /* Long-Descriptor Translation Table Level 1/2 Bits */
424 #define TTB_SECT_XN_MASK (1ULL << 54)
425 #define TTB_SECT_NG_MASK (1 << 11)
426 #define TTB_SECT_AF (1 << 10)
427 #define TTB_SECT_SH_MASK (3 << 8)
428 #define TTB_SECT_NS_MASK (1 << 5)
429 #define TTB_SECT_AP (1 << 6)
430 /* Note: TTB AP bits are set elsewhere */
431 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
432 #define TTB_SECT (1 << 0)
433 #define TTB_PAGETABLE (3 << 0)
434
435 /* TTBCR flags */
436 #define TTBCR_EAE (1 << 31)
437 #define TTBCR_T0SZ(x) ((x) << 0)
438 #define TTBCR_T1SZ(x) ((x) << 16)
439 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
440 #define TTBCR_IRGN0_NC (0 << 8)
441 #define TTBCR_IRGN0_WBWA (1 << 8)
442 #define TTBCR_IRGN0_WT (2 << 8)
443 #define TTBCR_IRGN0_WBNWA (3 << 8)
444 #define TTBCR_IRGN0_MASK (3 << 8)
445 #define TTBCR_ORGN0_NC (0 << 10)
446 #define TTBCR_ORGN0_WBWA (1 << 10)
447 #define TTBCR_ORGN0_WT (2 << 10)
448 #define TTBCR_ORGN0_WBNWA (3 << 10)
449 #define TTBCR_ORGN0_MASK (3 << 10)
450 #define TTBCR_SHARED_NON (0 << 12)
451 #define TTBCR_SHARED_OUTER (2 << 12)
452 #define TTBCR_SHARED_INNER (3 << 12)
453 #define TTBCR_EPD0 (0 << 7)
454
455 /*
456 * VMSAv8-32 Long-descriptor format memory region attributes
457 * (ARM Architecture Reference Manual section G5.7.4 [DDI0487E.a])
458 *
459 * MAIR0[ 7: 0] 0x00 Device-nGnRnE (aka Strongly-Ordered)
460 * MAIR0[15: 8] 0xaa Outer/Inner Write-Through, Read-Allocate No Write-Allocate
461 * MAIR0[23:16] 0xee Outer/Inner Write-Back, Read-Allocate No Write-Allocate
462 * MAIR0[31:24] 0xff Outer/Inner Write-Back, Read-Allocate Write-Allocate
463 */
464 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0xaa << (1 * 8)) | \
465 (0xee << (2 * 8)) | (0xff << (3 * 8)))
466
467 /* options available for data cache on each page */
468 enum dcache_option {
469 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
470 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
471 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
472 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
473 };
474 #elif defined(CONFIG_CPU_V7A)
475 /* Short-Descriptor Translation Table Level 1 Bits */
476 #define TTB_SECT_NS_MASK (1 << 19)
477 #define TTB_SECT_NG_MASK (1 << 17)
478 #define TTB_SECT_S_MASK (1 << 16)
479 /* Note: TTB AP bits are set elsewhere */
480 #define TTB_SECT_AP (3 << 10)
481 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
482 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
483 #define TTB_SECT_XN_MASK (1 << 4)
484 #define TTB_SECT_C_MASK (1 << 3)
485 #define TTB_SECT_B_MASK (1 << 2)
486 #define TTB_SECT (2 << 0)
487
488 /*
489 * Short-descriptor format memory region attributes, without TEX remap
490 * (ARM Architecture Reference Manual section G5.7.2 [DDI0487E.a])
491 *
492 * TEX[0] C B
493 * 0 0 0 Device-nGnRnE (aka Strongly-Ordered)
494 * 0 1 0 Outer/Inner Write-Through, Read-Allocate No Write-Allocate
495 * 0 1 1 Outer/Inner Write-Back, Read-Allocate No Write-Allocate
496 * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate
497 */
498 enum dcache_option {
499 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
500 DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
501 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
502 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
503 };
504 #else
505 #define TTB_SECT_AP (3 << 10)
506 /* options available for data cache on each page */
507 enum dcache_option {
508 DCACHE_OFF = 0x12,
509 DCACHE_WRITETHROUGH = 0x1a,
510 DCACHE_WRITEBACK = 0x1e,
511 DCACHE_WRITEALLOC = 0x16,
512 };
513 #endif
514
515 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
516 #define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
517 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
518 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
519 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
520 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
521 #endif
522
523 /* Size of an MMU section */
524 enum {
525 #ifdef CONFIG_ARMV7_LPAE
526 MMU_SECTION_SHIFT = 21, /* 2MB */
527 #else
528 MMU_SECTION_SHIFT = 20, /* 1MB */
529 #endif
530 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
531 };
532
533 #ifdef CONFIG_CPU_V7A
534 /* TTBR0 bits */
535 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
536 #define TTBR0_RGN_NC (0 << 3)
537 #define TTBR0_RGN_WBWA (1 << 3)
538 #define TTBR0_RGN_WT (2 << 3)
539 #define TTBR0_RGN_WB (3 << 3)
540 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
541 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
542 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
543 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
544 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
545 #endif
546
547 /**
548 * mmu_page_table_flush() - register an update to page tables
549 *
550 * Register an update to the page tables, and flush the TLB
551 *
552 * @start: start address of update in page table
553 * @stop: stop address of update in page table
554 */
555 void mmu_page_table_flush(unsigned long start, unsigned long stop);
556
557 #ifdef CONFIG_ARMV7_PSCI
558 void psci_arch_cpu_entry(void);
559 void psci_arch_init(void);
560 u32 psci_version(void);
561 s32 psci_features(u32 function_id, u32 psci_fid);
562 s32 psci_cpu_off(void);
563 s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
564 u32 context_id);
565 s32 psci_affinity_info(u32 function_id, u32 target_affinity,
566 u32 lowest_affinity_level);
567 u32 psci_migrate_info_type(void);
568 void psci_system_off(void);
569 void psci_system_reset(void);
570 #endif
571
572 #endif /* __ASSEMBLY__ */
573
574 #define arch_align_stack(x) (x)
575
576 #endif /* __KERNEL__ */
577
578 #endif /* CONFIG_ARM64 */
579
580 #ifndef __ASSEMBLY__
581 /**
582 * save_boot_params() - Save boot parameters before starting reset sequence
583 *
584 * If you provide this function it will be called immediately U-Boot starts,
585 * both for SPL and U-Boot proper.
586 *
587 * All registers are unchanged from U-Boot entry. No registers need be
588 * preserved.
589 *
590 * This is not a normal C function. There is no stack. Return by branching to
591 * save_boot_params_ret.
592 *
593 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
594 */
595
596 /**
597 * save_boot_params_ret() - Return from save_boot_params()
598 *
599 * If you provide save_boot_params(), then you should jump back to this
600 * function when done. Try to preserve all registers.
601 *
602 * If your implementation of save_boot_params() is in C then it is acceptable
603 * to simply call save_boot_params_ret() at the end of your function. Since
604 * there is no link register set up, you cannot just exit the function. U-Boot
605 * will return to the (initialised) value of lr, and likely crash/hang.
606 *
607 * If your implementation of save_boot_params() is in assembler then you
608 * should use 'b' or 'bx' to return to save_boot_params_ret.
609 */
610 void save_boot_params_ret(void);
611
612 /**
613 * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
614 *
615 * Change the virt/phys mapping and cache settings for a region.
616 *
617 * @virt: virtual start address of memory region to change
618 * @phys: physical address for the memory region to set
619 * @size: size of memory region to change
620 * @option: dcache option to select
621 */
622 void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
623 size_t size, enum dcache_option option);
624
625 /**
626 * mmu_set_region_dcache_behaviour() - set cache settings
627 *
628 * Change the cache settings for a region.
629 *
630 * @start: start address of memory region to change
631 * @size: size of memory region to change
632 * @option: dcache option to select
633 */
634 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
635 enum dcache_option option);
636
637 #ifdef CONFIG_SYS_NONCACHED_MEMORY
638 /**
639 * noncached_init() - Initialize non-cached memory region
640 *
641 * Initialize non-cached memory area. This memory region will be typically
642 * located right below the malloc() area and mapped uncached in the MMU.
643 *
644 * It is called during the generic post-relocation init sequence.
645 *
646 * Return: 0 if OK
647 */
648 int noncached_init(void);
649
650 phys_addr_t noncached_alloc(size_t size, size_t align);
651 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
652
653 #endif /* __ASSEMBLY__ */
654
655 #endif
656