1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Microchip SFR (Special Function Registers) registers for SAMA7 family. 4 * 5 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Cristian Birsan <cristian.birsan@microchip.com> 8 */ 9 10 #ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H 11 #define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H 12 13 #define SAMA7_SFR_OHCIICR 0x00 /* OHCI INT Configuration Register */ 14 #define SAMA7_SFR_OHCIISR 0x04 /* OHCI INT Status Register */ 15 /* 0x08 ~ 0xe3: Reserved */ 16 #define SAMA7_SFR_WPMR 0xe4 /* Write Protection Mode Register */ 17 #define SAMA7_SFR_WPSR 0xe4 /* Write Protection Status Register */ 18 /* 0xec ~ 0x200b: Reserved */ 19 #define SAMA7_SFR_DEBUG 0x200c /* Debug Register */ 20 21 /* 0x2010 ~ 0x2027: Reserved */ 22 #define SAMA7_SFR_EHCIOHCI 0x2020 /* EHCI OHCI Clock Configuration Reg */ 23 24 #define SAMA7_SFR_HSS_AXI_QOS 0x2028 /* HSS AXI QOS Register */ 25 #define SAMA7_SFR_UDDRC 0x202c /* UDDRC Register */ 26 #define SAMA7_SFR_CAN_SRAM_SEL 0x2030 /* CAN SRAM Select. Register */ 27 /* 0x2034 ~ 0x203f: Reserved */ 28 29 #define SAMA7_SFR_UTMI0 0x2040 30 #define SAMA7_SFR_UTMI0R(x) (SAMA7_SFR_UTMI0 + 4 * (x)) 31 32 #define SAMA7_SFR_UTMI0R0 0x2040 /* UTMI0 Configuration Register */ 33 #define SAMA7_SFR_UTMI0R1 0x2044 /* UTMI1 Configuration Register */ 34 #define SAMA7_SFR_UTMI0R2 0x2048 /* UTMI2 Configuration Register */ 35 36 /* Field definitions */ 37 #define SAMA7_SFR_OHCIICR_ARIE BIT(0) 38 #define SAMA7_SFR_OHCIICR_APPSTART BIT(1) 39 #define SAMA7_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) 40 #define SAMA7_SFR_OHCIICR_USB_SUSPEND GENMASK(10, 8) 41 42 #define SAMA7_SFR_OHCIISR_RIS(x) BIT(x) 43 44 #define SAMA7_SFR_WPMR_WPEN BIT(0) 45 #define SAMA7_SFR_WPMR_KEY 0x53465200 /* SFR in ASCII*/ 46 #define SAMA7_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) 47 48 #define SAMA7_SFR_WPSR_WPSRC_MASK GENMASK(23, 8) 49 #define SAMA7_SFR_WPSR_WPVS_MASK BIT(0) 50 51 #define SAMA7_SFR_CAN_SRAM_UPPER(x) BIT(x) 52 53 #define SAMA7_SFR_UTMI_RX_VBUS BIT(25) /* VBUS Valid bit */ 54 #define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X BIT(23) /* TXPREEMPAMPTUNE 1x */ 55 #define SAMA7_SFR_UTMI_COMMONON BIT(3) /* PLL Common ON bit */ 56 57 #define SAMA7_SFR_EHCIOHCI_PHYCLK BIT(1) /* Alternate PHY Clk */ 58 59 #endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */ 60