1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Samsung Electronics
4  * Thomas Abraham <thomas.ab@samsung.com>
5  */
6 
7 #include <common.h>
8 #include <asm/armv8/mmu.h>
9 
10 #if IS_ENABLED(CONFIG_EXYNOS7420)
11 
12 static struct mm_region exynos7420_mem_map[] = {
13 	{
14 		.virt	= 0x10000000UL,
15 		.phys	= 0x10000000UL,
16 		.size	= 0x10000000UL,
17 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
18 				PTE_BLOCK_NON_SHARE |
19 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
20 	}, {
21 		.virt	= 0x40000000UL,
22 		.phys	= 0x40000000UL,
23 		.size	= 0x80000000UL,
24 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 				PTE_BLOCK_INNER_SHARE,
26 	}, {
27 		/* List terminator */
28 	},
29 };
30 
31 struct mm_region *mem_map = exynos7420_mem_map;
32 
33 #elif CONFIG_IS_ENABLED(EXYNOS7870)
34 
35 static struct mm_region exynos7870_mem_map[] = {
36 	{
37 		.virt	= 0x10000000UL,
38 		.phys	= 0x10000000UL,
39 		.size	= 0x10000000UL,
40 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
41 				PTE_BLOCK_NON_SHARE |
42 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
43 	},
44 	{
45 		.virt	= 0x40000000UL,
46 		.phys	= 0x40000000UL,
47 		.size	= 0x3E400000UL,
48 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
49 				PTE_BLOCK_INNER_SHARE,
50 	},
51 	{
52 		.virt	= 0x80000000UL,
53 		.phys	= 0x80000000UL,
54 		.size	= 0x40000000UL,
55 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
56 				PTE_BLOCK_INNER_SHARE,
57 	},
58 
59 	{
60 		/* List terminator */
61 	},
62 };
63 
64 struct mm_region *mem_map = exynos7870_mem_map;
65 
66 #elif CONFIG_IS_ENABLED(EXYNOS7880)
67 
68 static struct mm_region exynos7880_mem_map[] = {
69 	{
70 		.virt	= 0x10000000UL,
71 		.phys	= 0x10000000UL,
72 		.size	= 0x10000000UL,
73 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
74 				PTE_BLOCK_NON_SHARE |
75 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
76 	},
77 	{
78 		.virt	= 0x40000000UL,
79 		.phys	= 0x40000000UL,
80 		.size	= 0x3E400000UL,
81 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
82 				PTE_BLOCK_INNER_SHARE,
83 	},
84 	{
85 		.virt	= 0x80000000UL,
86 		.phys	= 0x80000000UL,
87 		.size	= 0x80000000UL,
88 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
89 				PTE_BLOCK_INNER_SHARE,
90 	},
91 
92 	{
93 		/* List terminator */
94 	},
95 };
96 
97 struct mm_region *mem_map = exynos7880_mem_map;
98 #endif
99