1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <bootm.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <init.h>
13 #include <log.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/mach-imx/boot_mode.h>
23 #include <imx_thermal.h>
24 #include <ipu_pixfmt.h>
25 #include <thermal.h>
26 #include <sata.h>
27 #include <dm/device-internal.h>
28 #include <dm/uclass-internal.h>
29
30 #ifdef CONFIG_FSL_ESDHC_IMX
31 #include <fsl_esdhc_imx.h>
32 #endif
33
34 static u32 reset_cause = -1;
35
get_imx_reset_cause(void)36 u32 get_imx_reset_cause(void)
37 {
38 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
39
40 if (reset_cause == -1) {
41 reset_cause = readl(&src_regs->srsr);
42 /* preserve the value for U-Boot proper */
43 #if !defined(CONFIG_SPL_BUILD)
44 writel(reset_cause, &src_regs->srsr);
45 #endif
46 }
47
48 return reset_cause;
49 }
50
51 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
get_reset_cause(void)52 static char *get_reset_cause(void)
53 {
54 switch (get_imx_reset_cause()) {
55 case 0x00001:
56 case 0x00011:
57 return "POR";
58 case 0x00004:
59 return "CSU";
60 case 0x00008:
61 return "IPP USER";
62 case 0x00010:
63 #ifdef CONFIG_MX7
64 return "WDOG1";
65 #else
66 return "WDOG";
67 #endif
68 case 0x00020:
69 return "JTAG HIGH-Z";
70 case 0x00040:
71 return "JTAG SW";
72 case 0x00080:
73 return "WDOG3";
74 #ifdef CONFIG_MX7
75 case 0x00100:
76 return "WDOG4";
77 case 0x00200:
78 return "TEMPSENSE";
79 #elif defined(CONFIG_IMX8M)
80 case 0x00100:
81 return "WDOG2";
82 case 0x00200:
83 return "TEMPSENSE";
84 #else
85 case 0x00100:
86 return "TEMPSENSE";
87 case 0x10000:
88 return "WARM BOOT";
89 #endif
90 default:
91 return "unknown reset";
92 }
93 }
94 #endif
95
96 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
97
get_imx_type(u32 imxtype)98 const char *get_imx_type(u32 imxtype)
99 {
100 switch (imxtype) {
101 case MXC_CPU_IMX8MP:
102 return "8MP[8]"; /* Quad-core version of the imx8mp */
103 case MXC_CPU_IMX8MPD:
104 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
105 case MXC_CPU_IMX8MPL:
106 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
107 case MXC_CPU_IMX8MP6:
108 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
109 case MXC_CPU_IMX8MPUL:
110 return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */
111 case MXC_CPU_IMX8MN:
112 return "8MNano Quad"; /* Quad-core version */
113 case MXC_CPU_IMX8MND:
114 return "8MNano Dual"; /* Dual-core version */
115 case MXC_CPU_IMX8MNS:
116 return "8MNano Solo"; /* Single-core version */
117 case MXC_CPU_IMX8MNL:
118 return "8MNano QuadLite"; /* Quad-core Lite version */
119 case MXC_CPU_IMX8MNDL:
120 return "8MNano DualLite"; /* Dual-core Lite version */
121 case MXC_CPU_IMX8MNSL:
122 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
123 case MXC_CPU_IMX8MNUQ:
124 return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
125 case MXC_CPU_IMX8MNUD:
126 return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
127 case MXC_CPU_IMX8MNUS:
128 return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
129 case MXC_CPU_IMX8MM:
130 return "8MMQ"; /* Quad-core version of the imx8mm */
131 case MXC_CPU_IMX8MML:
132 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
133 case MXC_CPU_IMX8MMD:
134 return "8MMD"; /* Dual-core version of the imx8mm */
135 case MXC_CPU_IMX8MMDL:
136 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
137 case MXC_CPU_IMX8MMS:
138 return "8MMS"; /* Single-core version of the imx8mm */
139 case MXC_CPU_IMX8MMSL:
140 return "8MMSL"; /* Single-core Lite version of the imx8mm */
141 case MXC_CPU_IMX8MQ:
142 return "8MQ"; /* Quad-core version of the imx8mq */
143 case MXC_CPU_IMX8MQL:
144 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
145 case MXC_CPU_IMX8MD:
146 return "8MD"; /* Dual-core version of the imx8mq */
147 case MXC_CPU_MX7S:
148 return "7S"; /* Single-core version of the mx7 */
149 case MXC_CPU_MX7D:
150 return "7D"; /* Dual-core version of the mx7 */
151 case MXC_CPU_MX6QP:
152 return "6QP"; /* Quad-Plus version of the mx6 */
153 case MXC_CPU_MX6DP:
154 return "6DP"; /* Dual-Plus version of the mx6 */
155 case MXC_CPU_MX6Q:
156 return "6Q"; /* Quad-core version of the mx6 */
157 case MXC_CPU_MX6D:
158 return "6D"; /* Dual-core version of the mx6 */
159 case MXC_CPU_MX6DL:
160 return "6DL"; /* Dual Lite version of the mx6 */
161 case MXC_CPU_MX6SOLO:
162 return "6SOLO"; /* Solo version of the mx6 */
163 case MXC_CPU_MX6SL:
164 return "6SL"; /* Solo-Lite version of the mx6 */
165 case MXC_CPU_MX6SLL:
166 return "6SLL"; /* SLL version of the mx6 */
167 case MXC_CPU_MX6SX:
168 return "6SX"; /* SoloX version of the mx6 */
169 case MXC_CPU_MX6UL:
170 return "6UL"; /* Ultra-Lite version of the mx6 */
171 case MXC_CPU_MX6ULL:
172 return "6ULL"; /* ULL version of the mx6 */
173 case MXC_CPU_MX6ULZ:
174 return "6ULZ"; /* ULZ version of the mx6 */
175 case MXC_CPU_MX51:
176 return "51";
177 case MXC_CPU_MX53:
178 return "53";
179 default:
180 return "??";
181 }
182 }
183
print_cpuinfo(void)184 int print_cpuinfo(void)
185 {
186 u32 cpurev;
187 __maybe_unused u32 max_freq;
188
189 cpurev = get_cpu_rev();
190
191 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
192 struct udevice *thermal_dev;
193 int cpu_tmp, minc, maxc, ret;
194
195 printf("CPU: Freescale i.MX%s rev%d.%d",
196 get_imx_type((cpurev & 0x1FF000) >> 12),
197 (cpurev & 0x000F0) >> 4,
198 (cpurev & 0x0000F) >> 0);
199 max_freq = get_cpu_speed_grade_hz();
200 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
201 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
202 } else {
203 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
204 mxc_get_clock(MXC_ARM_CLK) / 1000000);
205 }
206 #else
207 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
208 get_imx_type((cpurev & 0x1FF000) >> 12),
209 (cpurev & 0x000F0) >> 4,
210 (cpurev & 0x0000F) >> 0,
211 mxc_get_clock(MXC_ARM_CLK) / 1000000);
212 #endif
213
214 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
215 puts("CPU: ");
216 switch (get_cpu_temp_grade(&minc, &maxc)) {
217 case TEMP_AUTOMOTIVE:
218 puts("Automotive temperature grade ");
219 break;
220 case TEMP_INDUSTRIAL:
221 puts("Industrial temperature grade ");
222 break;
223 case TEMP_EXTCOMMERCIAL:
224 puts("Extended Commercial temperature grade ");
225 break;
226 default:
227 puts("Commercial temperature grade ");
228 break;
229 }
230 printf("(%dC to %dC)", minc, maxc);
231 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
232 if (!ret) {
233 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
234
235 if (!ret)
236 printf(" at %dC", cpu_tmp);
237 else
238 debug(" - invalid sensor data\n");
239 } else {
240 debug(" - invalid sensor device\n");
241 }
242 puts("\n");
243 #endif
244
245 printf("Reset cause: %s\n", get_reset_cause());
246 return 0;
247 }
248 #endif
249
cpu_eth_init(struct bd_info * bis)250 int cpu_eth_init(struct bd_info *bis)
251 {
252 int rc = -ENODEV;
253
254 #if defined(CONFIG_FEC_MXC)
255 rc = fecmxc_initialize(bis);
256 #endif
257
258 return rc;
259 }
260
261 #ifdef CONFIG_FSL_ESDHC_IMX
262 /*
263 * Initializes on-chip MMC controllers.
264 * to override, implement board_mmc_init()
265 */
cpu_mmc_init(struct bd_info * bis)266 int cpu_mmc_init(struct bd_info *bis)
267 {
268 return fsl_esdhc_mmc_init(bis);
269 }
270 #endif
271
272 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
get_ahb_clk(void)273 u32 get_ahb_clk(void)
274 {
275 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
276 u32 reg, ahb_podf;
277
278 reg = __raw_readl(&imx_ccm->cbcdr);
279 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
280 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
281
282 return get_periph_clk() / (ahb_podf + 1);
283 }
284 #endif
285
arch_preboot_os(void)286 void arch_preboot_os(void)
287 {
288 #if defined(CONFIG_IMX_AHCI)
289 struct udevice *dev;
290 int rc;
291
292 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
293 if (!rc && dev) {
294 rc = device_remove(dev, DM_REMOVE_NORMAL);
295 if (rc)
296 printf("Cannot remove SATA device '%s' (err=%d)\n",
297 dev->name, rc);
298 }
299 #endif
300
301 #if defined(CONFIG_SATA)
302 if (!is_mx6sdl()) {
303 sata_remove(0);
304 #if defined(CONFIG_MX6)
305 disable_sata_clock();
306 #endif
307 }
308 #endif
309 #if defined(CONFIG_VIDEO_IPUV3)
310 /* disable video before launching O/S */
311 ipuv3_fb_shutdown();
312 #endif
313 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
314 lcdif_power_down();
315 #endif
316 }
317
318 #ifndef CONFIG_IMX8M
set_chipselect_size(int const cs_size)319 void set_chipselect_size(int const cs_size)
320 {
321 unsigned int reg;
322 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
323 reg = readl(&iomuxc_regs->gpr[1]);
324
325 switch (cs_size) {
326 case CS0_128:
327 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
328 reg |= 0x5;
329 break;
330 case CS0_64M_CS1_64M:
331 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
332 reg |= 0x1B;
333 break;
334 case CS0_64M_CS1_32M_CS2_32M:
335 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
336 reg |= 0x4B;
337 break;
338 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
339 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
340 reg |= 0x249;
341 break;
342 default:
343 printf("Unknown chip select size: %d\n", cs_size);
344 break;
345 }
346
347 writel(reg, &iomuxc_regs->gpr[1]);
348 }
349 #endif
350
351 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
352 /*
353 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
354 * defines a 2-bit SPEED_GRADING
355 */
356 #define OCOTP_TESTER3_SPEED_SHIFT 8
357 enum cpu_speed {
358 OCOTP_TESTER3_SPEED_GRADE0,
359 OCOTP_TESTER3_SPEED_GRADE1,
360 OCOTP_TESTER3_SPEED_GRADE2,
361 OCOTP_TESTER3_SPEED_GRADE3,
362 OCOTP_TESTER3_SPEED_GRADE4,
363 };
364
get_cpu_speed_grade_hz(void)365 u32 get_cpu_speed_grade_hz(void)
366 {
367 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
368 struct fuse_bank *bank = &ocotp->bank[1];
369 struct fuse_bank1_regs *fuse =
370 (struct fuse_bank1_regs *)bank->fuse_regs;
371 uint32_t val;
372
373 val = readl(&fuse->tester3);
374 val >>= OCOTP_TESTER3_SPEED_SHIFT;
375
376 if (is_imx8mn() || is_imx8mp()) {
377 val &= 0xf;
378 return 2300000000 - val * 100000000;
379 }
380
381 if (is_imx8mm())
382 val &= 0x7;
383 else
384 val &= 0x3;
385
386 switch(val) {
387 case OCOTP_TESTER3_SPEED_GRADE0:
388 return 800000000;
389 case OCOTP_TESTER3_SPEED_GRADE1:
390 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
391 case OCOTP_TESTER3_SPEED_GRADE2:
392 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
393 case OCOTP_TESTER3_SPEED_GRADE3:
394 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
395 case OCOTP_TESTER3_SPEED_GRADE4:
396 return 2000000000;
397 }
398
399 return 0;
400 }
401
402 /*
403 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
404 * defines a 2-bit SPEED_GRADING
405 */
406 #define OCOTP_TESTER3_TEMP_SHIFT 6
407
408 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
409 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
410
get_cpu_temp_grade(int * minc,int * maxc)411 u32 get_cpu_temp_grade(int *minc, int *maxc)
412 {
413 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
414 struct fuse_bank *bank = &ocotp->bank[1];
415 struct fuse_bank1_regs *fuse =
416 (struct fuse_bank1_regs *)bank->fuse_regs;
417 uint32_t val;
418
419 val = readl(&fuse->tester3);
420 if (is_imx8mp())
421 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
422 else
423 val >>= OCOTP_TESTER3_TEMP_SHIFT;
424 val &= 0x3;
425
426 if (minc && maxc) {
427 if (val == TEMP_AUTOMOTIVE) {
428 *minc = -40;
429 *maxc = 125;
430 } else if (val == TEMP_INDUSTRIAL) {
431 *minc = -40;
432 *maxc = 105;
433 } else if (val == TEMP_EXTCOMMERCIAL) {
434 *minc = -20;
435 *maxc = 105;
436 } else {
437 *minc = 0;
438 *maxc = 95;
439 }
440 }
441 return val;
442 }
443 #endif
444
445 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
get_boot_device(void)446 enum boot_device get_boot_device(void)
447 {
448 struct bootrom_sw_info **p =
449 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
450
451 enum boot_device boot_dev = SD1_BOOT;
452 u8 boot_type = (*p)->boot_dev_type;
453 u8 boot_instance = (*p)->boot_dev_instance;
454
455 switch (boot_type) {
456 case BOOT_TYPE_SD:
457 boot_dev = boot_instance + SD1_BOOT;
458 break;
459 case BOOT_TYPE_MMC:
460 boot_dev = boot_instance + MMC1_BOOT;
461 break;
462 case BOOT_TYPE_NAND:
463 boot_dev = NAND_BOOT;
464 break;
465 case BOOT_TYPE_QSPI:
466 boot_dev = QSPI_BOOT;
467 break;
468 case BOOT_TYPE_WEIM:
469 boot_dev = WEIM_NOR_BOOT;
470 break;
471 case BOOT_TYPE_SPINOR:
472 boot_dev = SPI_NOR_BOOT;
473 break;
474 case BOOT_TYPE_USB:
475 boot_dev = USB_BOOT;
476 break;
477 default:
478 #ifdef CONFIG_IMX8M
479 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
480 boot_dev = QSPI_BOOT;
481 #endif
482 break;
483 }
484
485 return boot_dev;
486 }
487 #endif
488
489 #ifdef CONFIG_NXP_BOARD_REVISION
nxp_board_rev(void)490 int nxp_board_rev(void)
491 {
492 /*
493 * Get Board ID information from OCOTP_GP1[15:8]
494 * RevA: 0x1
495 * RevB: 0x2
496 * RevC: 0x3
497 */
498 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
499 struct fuse_bank *bank = &ocotp->bank[4];
500 struct fuse_bank4_regs *fuse =
501 (struct fuse_bank4_regs *)bank->fuse_regs;
502
503 return (readl(&fuse->gp1) >> 8 & 0x0F);
504 }
505
nxp_board_rev_string(void)506 char nxp_board_rev_string(void)
507 {
508 const char *rev = "A";
509
510 return (*rev + nxp_board_rev() - 1);
511 }
512 #endif
513
reset_cpu(void)514 __weak void reset_cpu(void)
515 {
516 }
517