1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright 2021 NXP
4 */
5
6 #include <log.h>
7 #include <asm/io.h>
8 #include <asm/arch/imx-regs.h>
9 #include <linux/delay.h>
10
11 #include "upower_api.h"
12
13 #define UPOWER_AP_MU1_ADDR 0x29280000
14
15 #define PS_RTD BIT(0)
16 #define PS_DSP BIT(1)
17 #define PS_A35_0 BIT(2)
18 #define PS_A35_1 BIT(3)
19 #define PS_L2 BIT(4)
20 #define PS_FAST_NIC BIT(5)
21 #define PS_APD_PERIPH BIT(6)
22 #define PS_GPU3D BIT(7)
23 #define PS_HIFI4 BIT(8)
24 #define PS_DDR GENMASK(12, 9)
25 #define PS_PXP_EPDC BIT(13)
26 #define PS_MIPI_DSI BIT(14)
27 #define PS_MIPI_CSI BIT(15)
28 #define PS_NIC_LPAV BIT(16)
29 #define PS_FUSION_AO BIT(17)
30 #define PS_FUSE BIT(18)
31 #define PS_UPOWER BIT(19)
32
33 static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR;
34
upower_wait_resp(void)35 void upower_wait_resp(void)
36 {
37 while (!(readl(&muptr->rsr) & BIT(0))) {
38 debug("%s: poll the mu:%x\n", __func__, readl(&muptr->rsr));
39 udelay(100);
40 }
41
42 upwr_txrx_isr();
43 }
44
upower_status(int status)45 u32 upower_status(int status)
46 {
47 u32 ret = -1;
48
49 switch (status) {
50 case 0:
51 debug("%s: finished successfully!\n", __func__);
52 ret = 0;
53 break;
54 case -1:
55 printf("%s: memory allocation or resource failed!\n", __func__);
56 break;
57 case -2:
58 printf("%s: invalid argument!\n", __func__);
59 break;
60 case -3:
61 printf("%s: called in an invalid API state!\n", __func__);
62 break;
63 default:
64 printf("%s: invalid return status\n", __func__);
65 break;
66 }
67 return ret;
68 }
69
user_upwr_rdy_callb(u32 soc,u32 vmajor,u32 vminor)70 void user_upwr_rdy_callb(u32 soc, u32 vmajor, u32 vminor)
71 {
72 printf("%s: soc=%x\n", __func__, soc);
73 printf("%s: RAM version:%d.%d\n", __func__, vmajor, vminor);
74 }
75
upower_pmic_i2c_write(u32 reg_addr,u32 reg_val)76 int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val)
77 {
78 int ret, ret_val;
79 enum upwr_resp err_code;
80
81 ret = upwr_xcp_i2c_access(0x32, 1, 1, reg_addr, reg_val, NULL);
82 if (ret) {
83 printf("pmic i2c write failed ret %d\n", ret);
84 return ret;
85 }
86
87 upower_wait_resp();
88 ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
89 if (ret != UPWR_REQ_OK) {
90 printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
91 return ret;
92 }
93
94 debug("PMIC write reg[0x%x], val[0x%x]\n", reg_addr, reg_val);
95
96 return 0;
97 }
98
upower_pmic_i2c_read(u32 reg_addr,u32 * reg_val)99 int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val)
100 {
101 int ret, ret_val;
102 enum upwr_resp err_code;
103
104 if (!reg_val)
105 return -1;
106
107 ret = upwr_xcp_i2c_access(0x32, -1, 1, reg_addr, 0, NULL);
108 if (ret) {
109 printf("pmic i2c read failed ret %d\n", ret);
110 return ret;
111 }
112
113 upower_wait_resp();
114 ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
115 if (ret != UPWR_REQ_OK) {
116 printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
117 return ret;
118 }
119
120 *reg_val = ret_val;
121
122 debug("PMIC read reg[0x%x], val[0x%x]\n", reg_addr, *reg_val);
123
124 return 0;
125 }
126
upower_init(void)127 int upower_init(void)
128 {
129 u32 fw_major, fw_minor, fw_vfixes;
130 u32 soc_id;
131 int status;
132 enum upwr_resp err_code;
133
134 u32 swton;
135 u64 memon;
136 int ret, ret_val;
137
138 do {
139 status = upwr_init(1, muptr);
140 if (upower_status(status)) {
141 printf("%s: upower init failure\n", __func__);
142 break;
143 }
144
145 soc_id = upwr_rom_version(&fw_major, &fw_minor, &fw_vfixes);
146 if (!soc_id) {
147 printf("%s:, soc_id not initialized\n", __func__);
148 break;
149 }
150
151 printf("%s: soc_id=%d\n", __func__, soc_id);
152 printf("%s: version:%d.%d.%d\n", __func__, fw_major, fw_minor, fw_vfixes);
153
154 printf("%s: start uPower RAM service\n", __func__);
155 status = upwr_start(1, user_upwr_rdy_callb);
156 upower_wait_resp();
157 if (upower_status(status)) {
158 printf("%s: upower init failure\n", __func__);
159 break;
160 }
161 } while (0);
162
163 swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR |
164 PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI;
165 ret = upwr_pwm_power_on(&swton, NULL, NULL);
166 if (ret)
167 printf("Turn on switches fail %d\n", ret);
168 else
169 printf("Turning on switches...\n");
170
171 upower_wait_resp();
172 ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
173 if (ret != UPWR_REQ_OK)
174 printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
175 else
176 printf("Turn on switches ok\n");
177
178 /*
179 * Ascending Order -> bit [0:54)
180 * CA35 Core 0 L1 cache
181 * CA35 Core 1 L1 cache
182 * L2 Cache 0
183 * L2 Cache 1
184 * L2 Cache victim/tag
185 * CAAM Secure RAM
186 * DMA1 RAM
187 * FlexSPI2 FIFO, Buffer
188 * SRAM0
189 * AD ROM
190 * USB0 TX/RX RAM
191 * uSDHC0 FIFO RAM
192 * uSDHC1 FIFO RAM
193 * uSDHC2 FIFO and USB1 TX/RX RAM
194 * GIC RAM
195 * ENET TX FIXO
196 * Reserved(Brainshift)
197 * DCNano Tile2Linear and RGB Correction
198 * DCNano Cursor and FIFO
199 * EPDC LUT
200 * EPDC FIFO
201 * DMA2 RAM
202 * GPU2D RAM Group 1
203 * GPU2D RAM Group 2
204 * GPU3D RAM Group 1
205 * GPU3D RAM Group 2
206 * HIFI4 Caches, IRAM, DRAM
207 * ISI Buffers
208 * MIPI-CSI FIFO
209 * MIPI-DSI FIFO
210 * PXP Caches, Buffers
211 * SRAM1
212 * Casper RAM
213 * DMA0 RAM
214 * FlexCAN RAM
215 * FlexSPI0 FIFO, Buffer
216 * FlexSPI1 FIFO, Buffer
217 * CM33 Cache
218 * PowerQuad RAM
219 * ETF RAM
220 * Sentinel PKC, Data RAM1, Inst RAM0/1
221 * Sentinel ROM
222 * uPower IRAM/DRAM
223 * uPower ROM
224 * CM33 ROM
225 * SSRAM Partition 0
226 * SSRAM Partition 1
227 * SSRAM Partition 2,3,4
228 * SSRAM Partition 5
229 * SSRAM Partition 6
230 * SSRAM Partition 7_a(128KB)
231 * SSRAM Partition 7_b(64KB)
232 * SSRAM Partition 7_c(64KB)
233 * Sentinel Data RAM0, Inst RAM2
234 */
235 /* MIPI-CSI FIFO BIT28 not set */
236 memon = 0x3FFFFFEFFFFFFCUL;
237 ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon, NULL);
238 if (ret)
239 printf("Turn on memories fail %d\n", ret);
240 else
241 printf("Turning on memories...\n");
242
243 upower_wait_resp();
244 ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
245 if (ret != UPWR_REQ_OK)
246 printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
247 else
248 printf("Turn on memories ok\n");
249
250 mdelay(1);
251
252 ret = upwr_xcp_set_ddr_retention(APD_DOMAIN, 0, NULL);
253 if (ret)
254 printf("Clear DDR retention fail %d\n", ret);
255 else
256 printf("Clearing DDR retention...\n");
257
258 upower_wait_resp();
259 ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
260 if (ret != UPWR_REQ_OK)
261 printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
262 else
263 printf("Clear DDR retention ok\n");
264
265 return 0;
266 }
267