1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 */
6
7 #include <common.h>
8 #include <hang.h>
9 #include <log.h>
10 #include <linux/delay.h>
11 #include <linux/types.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/io.h>
16 #include <asm/types.h>
17 #include <wait_bit.h>
18
19 #if defined(CONFIG_MX6_DDRCAL)
reset_read_data_fifos(void)20 static void reset_read_data_fifos(void)
21 {
22 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
23
24 /* Reset data FIFOs twice. */
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
27
28 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
29 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
30 }
31
precharge_all(const bool cs0_enable,const bool cs1_enable)32 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
33 {
34 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
35
36 /*
37 * Issue the Precharge-All command to the DDR device for both
38 * chip selects. Note, CON_REQ bit should also remain set. If
39 * only using one chip select, then precharge only the desired
40 * chip select.
41 */
42 if (cs0_enable) { /* CS0 */
43 writel(0x04008050, &mmdc0->mdscr);
44 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
45 }
46
47 if (cs1_enable) { /* CS1 */
48 writel(0x04008058, &mmdc0->mdscr);
49 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
50 }
51 }
52
force_delay_measurement(int bus_size)53 static void force_delay_measurement(int bus_size)
54 {
55 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
56 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
57
58 writel(0x800, &mmdc0->mpmur0);
59 if (bus_size == 0x2)
60 writel(0x800, &mmdc1->mpmur0);
61 }
62
modify_dg_result(u32 * reg_st0,u32 * reg_st1,u32 * reg_ctrl)63 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
64 {
65 u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
66
67 /*
68 * DQS gating absolute offset should be modified from reflecting
69 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
70 */
71
72 val_ctrl = readl(reg_ctrl);
73 val_ctrl &= 0xf0000000;
74
75 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
76 dg_dl_abs_offset = dg_tmp_val & 0x7f;
77 dg_hc_del = (dg_tmp_val & 0x780) << 1;
78
79 val_ctrl |= dg_dl_abs_offset + dg_hc_del;
80
81 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
82 dg_dl_abs_offset = dg_tmp_val & 0x7f;
83 dg_hc_del = (dg_tmp_val & 0x780) << 1;
84
85 val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
86
87 writel(val_ctrl, reg_ctrl);
88 }
89
correct_mpwldectr_result(void * reg)90 static void correct_mpwldectr_result(void *reg)
91 {
92 /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
93 const unsigned int limit = 0x148;
94 u32 val = readl(reg);
95 u32 old = val;
96
97 if ((val & 0x17f) > limit)
98 val &= 0xffff << 16;
99
100 if (((val >> 16) & 0x17f) > limit)
101 val &= 0xffff;
102
103 if (old != val)
104 writel(val, reg);
105 }
106
mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const * sysinfo)107 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
108 {
109 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
110 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
111 u32 esdmisc_val, zq_val, mdmisc_val;
112 u32 errors = 0;
113 u32 ldectrl[4] = {0};
114 u32 ddr_mr1 = 0x4;
115 u32 rwalat_max;
116
117 /*
118 * Stash old values in case calibration fails,
119 * we need to restore them
120 */
121 ldectrl[0] = readl(&mmdc0->mpwldectrl0);
122 ldectrl[1] = readl(&mmdc0->mpwldectrl1);
123 if (sysinfo->dsize == 2) {
124 ldectrl[2] = readl(&mmdc1->mpwldectrl0);
125 ldectrl[3] = readl(&mmdc1->mpwldectrl1);
126 }
127
128 /* disable DDR logic power down timer */
129 clrbits_le32(&mmdc0->mdpdc, 0xff00);
130
131 /* disable Adopt power down timer */
132 setbits_le32(&mmdc0->mapsr, 0x1);
133
134 /* Save old RALAT and WALAT values */
135 mdmisc_val = readl(&mmdc0->mdmisc);
136
137 debug("Starting write leveling calibration.\n");
138
139 /*
140 * 2. disable auto refresh and ZQ calibration
141 * before proceeding with Write Leveling calibration
142 */
143 esdmisc_val = readl(&mmdc0->mdref);
144 writel(0x0000C000, &mmdc0->mdref);
145 zq_val = readl(&mmdc0->mpzqhwctrl);
146 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
147
148 /* 3. increase walat and ralat to maximum */
149 rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
150 setbits_le32(&mmdc0->mdmisc, rwalat_max);
151 if (sysinfo->dsize == 2)
152 setbits_le32(&mmdc1->mdmisc, rwalat_max);
153 /*
154 * 4 & 5. Configure the external DDR device to enter write-leveling
155 * mode through Load Mode Register command.
156 * Register setting:
157 * Bits[31:16] MR1 value (0x0080 write leveling enable)
158 * Bit[9] set WL_EN to enable MMDC DQS output
159 * Bits[6:4] set CMD bits for Load Mode Register programming
160 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
161 */
162 writel(0x00808231, &mmdc0->mdscr);
163
164 /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
165 writel(0x00000001, &mmdc0->mpwlgcr);
166
167 /*
168 * 7. Upon completion of this process the MMDC de-asserts
169 * the MPWLGCR[HW_WL_EN]
170 */
171 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
172
173 /*
174 * 8. check for any errors: check both PHYs for x64 configuration,
175 * if x32, check only PHY0
176 */
177 if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
178 errors |= 1;
179 if (sysinfo->dsize == 2)
180 if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
181 errors |= 2;
182
183 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
184
185 /* check to see if cal failed */
186 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
187 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
188 ((sysinfo->dsize < 2) ||
189 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
190 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
191 debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
192 writel(ldectrl[0], &mmdc0->mpwldectrl0);
193 writel(ldectrl[1], &mmdc0->mpwldectrl1);
194 if (sysinfo->dsize == 2) {
195 writel(ldectrl[2], &mmdc1->mpwldectrl0);
196 writel(ldectrl[3], &mmdc1->mpwldectrl1);
197 }
198 errors |= 4;
199 }
200
201 correct_mpwldectr_result(&mmdc0->mpwldectrl0);
202 correct_mpwldectr_result(&mmdc0->mpwldectrl1);
203 if (sysinfo->dsize == 2) {
204 correct_mpwldectr_result(&mmdc1->mpwldectrl0);
205 correct_mpwldectr_result(&mmdc1->mpwldectrl1);
206 }
207
208 /*
209 * User should issue MRS command to exit write leveling mode
210 * through Load Mode Register command
211 * Register setting:
212 * Bits[31:16] MR1 value "ddr_mr1" value from initialization
213 * Bit[9] clear WL_EN to disable MMDC DQS output
214 * Bits[6:4] set CMD bits for Load Mode Register programming
215 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
216 */
217 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
218
219 /* re-enable auto refresh and zq cal */
220 writel(esdmisc_val, &mmdc0->mdref);
221 writel(zq_val, &mmdc0->mpzqhwctrl);
222
223 /* restore WALAT/RALAT */
224 writel(mdmisc_val, &mmdc0->mdmisc);
225
226 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
227 readl(&mmdc0->mpwldectrl0));
228 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
229 readl(&mmdc0->mpwldectrl1));
230 if (sysinfo->dsize == 2) {
231 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
232 readl(&mmdc1->mpwldectrl0));
233 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
234 readl(&mmdc1->mpwldectrl1));
235 }
236
237 /* We must force a readback of these values, to get them to stick */
238 readl(&mmdc0->mpwldectrl0);
239 readl(&mmdc0->mpwldectrl1);
240 if (sysinfo->dsize == 2) {
241 readl(&mmdc1->mpwldectrl0);
242 readl(&mmdc1->mpwldectrl1);
243 }
244
245 /* enable DDR logic power down timer: */
246 setbits_le32(&mmdc0->mdpdc, 0x00005500);
247
248 /* Enable Adopt power down timer: */
249 clrbits_le32(&mmdc0->mapsr, 0x1);
250
251 /* Clear CON_REQ */
252 writel(0, &mmdc0->mdscr);
253
254 return errors;
255 }
256
mmdc_set_sdqs(bool set)257 static void mmdc_set_sdqs(bool set)
258 {
259 struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
260 (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
261 struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
262 (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
263 struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
264 (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
265 struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
266 (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
267 struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
268 (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
269 int i, sdqs_cnt;
270 u32 sdqs;
271
272 if (is_mx6sx()) {
273 sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
274 sdqs_cnt = 2;
275 } else if (is_mx6sl()) {
276 sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
277 sdqs_cnt = 2;
278 } else if (is_mx6ul() || is_mx6ull()) {
279 sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
280 sdqs_cnt = 2;
281 } else if (is_mx6sdl()) {
282 sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
283 sdqs_cnt = 8;
284 } else { /* MX6DQ */
285 sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
286 sdqs_cnt = 8;
287 }
288
289 for (i = 0; i < sdqs_cnt; i++) {
290 if (set)
291 setbits_le32(sdqs + (4 * i), 0x7000);
292 else
293 clrbits_le32(sdqs + (4 * i), 0x7000);
294 }
295 }
296
mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const * sysinfo)297 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
298 {
299 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
300 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
301 bool cs0_enable;
302 bool cs1_enable;
303 bool cs0_enable_initial;
304 bool cs1_enable_initial;
305 u32 esdmisc_val;
306 u32 temp_ref;
307 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
308 u32 errors = 0;
309 u32 initdelay = 0x40404040;
310
311 /* check to see which chip selects are enabled */
312 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
313 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
314
315 /* disable DDR logic power down timer: */
316 clrbits_le32(&mmdc0->mdpdc, 0xff00);
317
318 /* disable Adopt power down timer: */
319 setbits_le32(&mmdc0->mapsr, 0x1);
320
321 /* set DQS pull ups */
322 mmdc_set_sdqs(true);
323
324 /* Save old RALAT and WALAT values */
325 esdmisc_val = readl(&mmdc0->mdmisc);
326
327 setbits_le32(&mmdc0->mdmisc,
328 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
329
330 /* Disable auto refresh before proceeding with calibration */
331 temp_ref = readl(&mmdc0->mdref);
332 writel(0x0000c000, &mmdc0->mdref);
333
334 /*
335 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
336 * this also sets the CON_REQ bit.
337 */
338 if (cs0_enable_initial)
339 writel(0x00008020, &mmdc0->mdscr);
340 if (cs1_enable_initial)
341 writel(0x00008028, &mmdc0->mdscr);
342
343 /* poll to make sure the con_ack bit was asserted */
344 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
345
346 /*
347 * Check MDMISC register CALIB_PER_CS to see which CS calibration
348 * is targeted to (under normal cases, it should be cleared
349 * as this is the default value, indicating calibration is directed
350 * to CS0).
351 * Disable the other chip select not being target for calibration
352 * to avoid any potential issues. This will get re-enabled at end
353 * of calibration.
354 */
355 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
356 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
357 else
358 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
359
360 /*
361 * Check to see which chip selects are now enabled for
362 * the remainder of the calibration.
363 */
364 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
365 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
366
367 precharge_all(cs0_enable, cs1_enable);
368
369 /* Write the pre-defined value into MPPDCMPR1 */
370 writel(pddword, &mmdc0->mppdcmpr1);
371
372 /*
373 * Issue a write access to the external DDR device by setting
374 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
375 * this bit until it clears to indicate completion of the write access.
376 */
377 setbits_le32(&mmdc0->mpswdar0, 1);
378 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
379
380 /* Set the RD_DL_ABS# bits to their default values
381 * (will be calibrated later in the read delay-line calibration).
382 * Both PHYs for x64 configuration, if x32, do only PHY0.
383 */
384 writel(initdelay, &mmdc0->mprddlctl);
385 if (sysinfo->dsize == 0x2)
386 writel(initdelay, &mmdc1->mprddlctl);
387
388 /* Force a measurment, for previous delay setup to take effect. */
389 force_delay_measurement(sysinfo->dsize);
390
391 /*
392 * ***************************
393 * Read DQS Gating calibration
394 * ***************************
395 */
396 debug("Starting Read DQS Gating calibration.\n");
397
398 /*
399 * Reset the read data FIFOs (two resets); only need to issue reset
400 * to PHY0 since in x64 mode, the reset will also go to PHY1.
401 */
402 reset_read_data_fifos();
403
404 /*
405 * Start the automatic read DQS gating calibration process by
406 * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
407 * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
408 * to indicate completion.
409 * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
410 * no errors were seen during calibration.
411 */
412
413 /*
414 * Set bit 30: chooses option to wait 32 cycles instead of
415 * 16 before comparing read data.
416 */
417 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
418 if (sysinfo->dsize == 2)
419 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
420
421 /* Set bit 28 to start automatic read DQS gating calibration */
422 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
423
424 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
425 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
426
427 /*
428 * Check to see if any errors were encountered during calibration
429 * (check MPDGCTRL0[HW_DG_ERR]).
430 * Check both PHYs for x64 configuration, if x32, check only PHY0.
431 */
432 if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
433 errors |= 1;
434
435 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
436 errors |= 2;
437
438 /* now disable mpdgctrl0[DG_CMP_CYC] */
439 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
440 if (sysinfo->dsize == 2)
441 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
442
443 /*
444 * DQS gating absolute offset should be modified from
445 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
446 * reflecting (HW_DG_UPx - 0x80)
447 */
448 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
449 &mmdc0->mpdgctrl0);
450 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
451 &mmdc0->mpdgctrl1);
452 if (sysinfo->dsize == 0x2) {
453 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
454 &mmdc1->mpdgctrl0);
455 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
456 &mmdc1->mpdgctrl1);
457 }
458 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
459
460 /*
461 * **********************
462 * Read Delay calibration
463 * **********************
464 */
465 debug("Starting Read Delay calibration.\n");
466
467 reset_read_data_fifos();
468
469 /*
470 * 4. Issue the Precharge-All command to the DDR device for both
471 * chip selects. If only using one chip select, then precharge
472 * only the desired chip select.
473 */
474 precharge_all(cs0_enable, cs1_enable);
475
476 /*
477 * 9. Read delay-line calibration
478 * Start the automatic read calibration process by asserting
479 * MPRDDLHWCTL[HW_RD_DL_EN].
480 */
481 writel(0x00000030, &mmdc0->mprddlhwctl);
482
483 /*
484 * 10. poll for completion
485 * MMDC indicates that the write data calibration had finished by
486 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
487 * no error bits were set.
488 */
489 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
490
491 /* check both PHYs for x64 configuration, if x32, check only PHY0 */
492 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
493 errors |= 4;
494
495 if ((sysinfo->dsize == 0x2) &&
496 (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
497 errors |= 8;
498
499 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
500
501 /*
502 * ***********************
503 * Write Delay Calibration
504 * ***********************
505 */
506 debug("Starting Write Delay calibration.\n");
507
508 reset_read_data_fifos();
509
510 /*
511 * 4. Issue the Precharge-All command to the DDR device for both
512 * chip selects. If only using one chip select, then precharge
513 * only the desired chip select.
514 */
515 precharge_all(cs0_enable, cs1_enable);
516
517 /*
518 * 8. Set the WR_DL_ABS# bits to their default values.
519 * Both PHYs for x64 configuration, if x32, do only PHY0.
520 */
521 writel(initdelay, &mmdc0->mpwrdlctl);
522 if (sysinfo->dsize == 0x2)
523 writel(initdelay, &mmdc1->mpwrdlctl);
524
525 /*
526 * XXX This isn't in the manual. Force a measurement,
527 * for previous delay setup to effect.
528 */
529 force_delay_measurement(sysinfo->dsize);
530
531 /*
532 * 9. 10. Start the automatic write calibration process
533 * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
534 */
535 writel(0x00000030, &mmdc0->mpwrdlhwctl);
536
537 /*
538 * Poll for completion.
539 * MMDC indicates that the write data calibration had finished
540 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
541 * Also, ensure that no error bits were set.
542 */
543 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
544
545 /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
546 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
547 errors |= 16;
548
549 if ((sysinfo->dsize == 0x2) &&
550 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
551 errors |= 32;
552
553 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
554
555 reset_read_data_fifos();
556
557 /* Enable DDR logic power down timer */
558 setbits_le32(&mmdc0->mdpdc, 0x00005500);
559
560 /* Enable Adopt power down timer */
561 clrbits_le32(&mmdc0->mapsr, 0x1);
562
563 /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
564 writel(esdmisc_val, &mmdc0->mdmisc);
565
566 /* Clear DQS pull ups */
567 mmdc_set_sdqs(false);
568
569 /* Re-enable SDE (chip selects) if they were set initially */
570 if (cs1_enable_initial)
571 /* Set SDE_1 */
572 setbits_le32(&mmdc0->mdctl, 1 << 30);
573
574 if (cs0_enable_initial)
575 /* Set SDE_0 */
576 setbits_le32(&mmdc0->mdctl, 1 << 31);
577
578 /* Re-enable to auto refresh */
579 writel(temp_ref, &mmdc0->mdref);
580
581 /* Clear the MDSCR (including the con_req bit) */
582 writel(0x0, &mmdc0->mdscr); /* CS0 */
583
584 /* Poll to make sure the con_ack bit is clear */
585 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
586
587 /*
588 * Print out the registers that were updated as a result
589 * of the calibration process.
590 */
591 debug("MMDC registers updated from calibration\n");
592 debug("Read DQS gating calibration:\n");
593 debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
594 debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
595 if (sysinfo->dsize == 2) {
596 debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
597 debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
598 }
599 debug("Read calibration:\n");
600 debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
601 if (sysinfo->dsize == 2)
602 debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
603 debug("Write calibration:\n");
604 debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
605 if (sysinfo->dsize == 2)
606 debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
607
608 /*
609 * Registers below are for debugging purposes. These print out
610 * the upper and lower boundaries captured during
611 * read DQS gating calibration.
612 */
613 debug("Status registers bounds for read DQS gating:\n");
614 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
615 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
616 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
617 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
618 if (sysinfo->dsize == 2) {
619 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
620 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
621 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
622 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
623 }
624
625 debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
626
627 return errors;
628 }
629 #endif
630
631 #if defined(CONFIG_MX6SX)
632 /* Configure MX6SX mmdc iomux */
mx6sx_dram_iocfg(unsigned width,const struct mx6sx_iomux_ddr_regs * ddr,const struct mx6sx_iomux_grp_regs * grp)633 void mx6sx_dram_iocfg(unsigned width,
634 const struct mx6sx_iomux_ddr_regs *ddr,
635 const struct mx6sx_iomux_grp_regs *grp)
636 {
637 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
638 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
639
640 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
641 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
642
643 /* DDR IO TYPE */
644 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
645 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
646
647 /* CLOCK */
648 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
649
650 /* ADDRESS */
651 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
652 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
653 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
654
655 /* Control */
656 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
657 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
658 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
659 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
660 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
661 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
662 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
663
664 /* Data Strobes */
665 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
666 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
667 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
668 if (width >= 32) {
669 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
670 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
671 }
672
673 /* Data */
674 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
675 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
676 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
677 if (width >= 32) {
678 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
679 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
680 }
681 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
682 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
683 if (width >= 32) {
684 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
685 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
686 }
687 }
688 #endif
689
690 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
mx6ul_dram_iocfg(unsigned width,const struct mx6ul_iomux_ddr_regs * ddr,const struct mx6ul_iomux_grp_regs * grp)691 void mx6ul_dram_iocfg(unsigned width,
692 const struct mx6ul_iomux_ddr_regs *ddr,
693 const struct mx6ul_iomux_grp_regs *grp)
694 {
695 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
696 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
697
698 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
699 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
700
701 /* DDR IO TYPE */
702 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
703 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
704
705 /* CLOCK */
706 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
707
708 /* ADDRESS */
709 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
710 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
711 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
712
713 /* Control */
714 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
715 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
716 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
717 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
718 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
719
720 /* Data Strobes */
721 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
722 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
723 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
724
725 /* Data */
726 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
727 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
728 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
729 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
730 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
731 }
732 #endif
733
734 #if defined(CONFIG_MX6SL)
mx6sl_dram_iocfg(unsigned width,const struct mx6sl_iomux_ddr_regs * ddr,const struct mx6sl_iomux_grp_regs * grp)735 void mx6sl_dram_iocfg(unsigned width,
736 const struct mx6sl_iomux_ddr_regs *ddr,
737 const struct mx6sl_iomux_grp_regs *grp)
738 {
739 struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
740 struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
741
742 mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
743 mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
744
745 /* DDR IO TYPE */
746 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
747 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
748
749 /* CLOCK */
750 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
751
752 /* ADDRESS */
753 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
754 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
755 mx6_grp_iomux->grp_addds = grp->grp_addds;
756
757 /* Control */
758 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
759 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
760 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
761
762 /* Data Strobes */
763 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
764 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
765 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
766 if (width >= 32) {
767 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
768 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
769 }
770
771 /* Data */
772 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
773 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
774 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
775 if (width >= 32) {
776 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
777 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
778 }
779
780 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
781 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
782 if (width >= 32) {
783 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
784 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
785 }
786 }
787 #endif
788
789 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
790 /* Configure MX6DQ mmdc iomux */
mx6dq_dram_iocfg(unsigned width,const struct mx6dq_iomux_ddr_regs * ddr,const struct mx6dq_iomux_grp_regs * grp)791 void mx6dq_dram_iocfg(unsigned width,
792 const struct mx6dq_iomux_ddr_regs *ddr,
793 const struct mx6dq_iomux_grp_regs *grp)
794 {
795 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
796 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
797
798 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
799 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
800
801 /* DDR IO Type */
802 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
803 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
804
805 /* Clock */
806 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
807 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
808
809 /* Address */
810 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
811 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
812 mx6_grp_iomux->grp_addds = grp->grp_addds;
813
814 /* Control */
815 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
816 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
817 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
818 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
819 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
820 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
821 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
822
823 /* Data Strobes */
824 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
825 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
826 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
827 if (width >= 32) {
828 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
829 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
830 }
831 if (width >= 64) {
832 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
833 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
834 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
835 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
836 }
837
838 /* Data */
839 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
840 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
841 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
842 if (width >= 32) {
843 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
844 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
845 }
846 if (width >= 64) {
847 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
848 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
849 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
850 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
851 }
852 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
853 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
854 if (width >= 32) {
855 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
856 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
857 }
858 if (width >= 64) {
859 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
860 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
861 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
862 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
863 }
864 }
865 #endif
866
867 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
868 /* Configure MX6SDL mmdc iomux */
mx6sdl_dram_iocfg(unsigned width,const struct mx6sdl_iomux_ddr_regs * ddr,const struct mx6sdl_iomux_grp_regs * grp)869 void mx6sdl_dram_iocfg(unsigned width,
870 const struct mx6sdl_iomux_ddr_regs *ddr,
871 const struct mx6sdl_iomux_grp_regs *grp)
872 {
873 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
874 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
875
876 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
877 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
878
879 /* DDR IO Type */
880 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
881 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
882
883 /* Clock */
884 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
885 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
886
887 /* Address */
888 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
889 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
890 mx6_grp_iomux->grp_addds = grp->grp_addds;
891
892 /* Control */
893 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
894 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
895 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
896 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
897 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
898 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
899 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
900
901 /* Data Strobes */
902 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
903 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
904 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
905 if (width >= 32) {
906 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
907 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
908 }
909 if (width >= 64) {
910 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
911 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
912 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
913 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
914 }
915
916 /* Data */
917 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
918 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
919 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
920 if (width >= 32) {
921 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
922 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
923 }
924 if (width >= 64) {
925 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
926 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
927 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
928 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
929 }
930 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
931 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
932 if (width >= 32) {
933 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
934 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
935 }
936 if (width >= 64) {
937 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
938 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
939 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
940 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
941 }
942 }
943 #endif
944
945 /*
946 * Configure mx6 mmdc registers based on:
947 * - board-specific memory configuration
948 * - board-specific calibration data
949 * - ddr3/lpddr2 chip details
950 *
951 * The various calculations here are derived from the Freescale
952 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
953 * MMDC configuration registers based on memory system and memory chip
954 * parameters.
955 *
956 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
957 * configuration registers based on memory system and memory chip
958 * parameters.
959 *
960 * The defaults here are those which were specified in the spreadsheet.
961 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
962 * and/or IMX6SLRM section titled MMDC initialization.
963 */
964 #define MR(val, ba, cmd, cs1) \
965 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
966 #define MMDC1(entry, value) do { \
967 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
968 mmdc1->entry = value; \
969 } while (0)
970
971 /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
972 #define BOOT_CFG3_DDR_MASK 0x30
973 #define BOOT_CFG3_EXT_DDR_MASK 0x33
974
975 #define DDR_MMAP_NOC_SINGLE 0
976 #define DDR_MMAP_NOC_DUAL 0x31
977
978 /* NoC ACTIVATE shifts */
979 #define NOC_RD_SHIFT 0
980 #define NOC_FAW_PERIOD_SHIFT 4
981 #define NOC_FAW_BANKS_SHIFT 10
982
983 /* NoC DdrTiming shifts */
984 #define NOC_ACT_TO_ACT_SHIFT 0
985 #define NOC_RD_TO_MISS_SHIFT 6
986 #define NOC_WR_TO_MISS_SHIFT 12
987 #define NOC_BURST_LEN_SHIFT 18
988 #define NOC_RD_TO_WR_SHIFT 21
989 #define NOC_WR_TO_RD_SHIFT 26
990 #define NOC_BW_RATIO_SHIFT 31
991
992 /*
993 * According JESD209-2B-LPDDR2: Table 103
994 * WL: write latency
995 */
lpddr2_wl(uint32_t mem_speed)996 static int lpddr2_wl(uint32_t mem_speed)
997 {
998 switch (mem_speed) {
999 case 1066:
1000 case 933:
1001 return 4;
1002 case 800:
1003 return 3;
1004 case 677:
1005 case 533:
1006 return 2;
1007 case 400:
1008 case 333:
1009 return 1;
1010 default:
1011 puts("invalid memory speed\n");
1012 hang();
1013 }
1014
1015 return 0;
1016 }
1017
1018 /*
1019 * According JESD209-2B-LPDDR2: Table 103
1020 * RL: read latency
1021 */
lpddr2_rl(uint32_t mem_speed)1022 static int lpddr2_rl(uint32_t mem_speed)
1023 {
1024 switch (mem_speed) {
1025 case 1066:
1026 return 8;
1027 case 933:
1028 return 7;
1029 case 800:
1030 return 6;
1031 case 677:
1032 return 5;
1033 case 533:
1034 return 4;
1035 case 400:
1036 case 333:
1037 return 3;
1038 default:
1039 puts("invalid memory speed\n");
1040 hang();
1041 }
1042
1043 return 0;
1044 }
1045
mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo * sysinfo,const struct mx6_mmdc_calibration * calib,const struct mx6_lpddr2_cfg * lpddr2_cfg)1046 void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1047 const struct mx6_mmdc_calibration *calib,
1048 const struct mx6_lpddr2_cfg *lpddr2_cfg)
1049 {
1050 volatile struct mmdc_p_regs *mmdc0;
1051 u32 val;
1052 u8 tcke, tcksrx, tcksre, trrd;
1053 u8 twl, txp, tfaw, tcl;
1054 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
1055 u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
1056 u16 cs0_end;
1057 u8 coladdr;
1058 int clkper; /* clock period in picoseconds */
1059 int clock; /* clock freq in mHz */
1060 int cs;
1061
1062 /* only support 16/32 bits */
1063 if (sysinfo->dsize > 1)
1064 hang();
1065
1066 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1067
1068 clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
1069 clkper = (1000 * 1000) / clock; /* pico seconds */
1070
1071 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
1072
1073 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
1074 switch (lpddr2_cfg->density) {
1075 case 1:
1076 case 2:
1077 case 4:
1078 trfc = DIV_ROUND_UP(130000, clkper) - 1;
1079 txsr = DIV_ROUND_UP(140000, clkper) - 1;
1080 break;
1081 case 8:
1082 trfc = DIV_ROUND_UP(210000, clkper) - 1;
1083 txsr = DIV_ROUND_UP(220000, clkper) - 1;
1084 break;
1085 default:
1086 /*
1087 * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
1088 */
1089 hang();
1090 break;
1091 }
1092 /*
1093 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
1094 * set them to 0. */
1095 txp = DIV_ROUND_UP(7500, clkper) - 1;
1096 tcke = 3;
1097 if (lpddr2_cfg->mem_speed == 333)
1098 tfaw = DIV_ROUND_UP(60000, clkper) - 1;
1099 else
1100 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1101 trrd = DIV_ROUND_UP(10000, clkper) - 1;
1102
1103 /* tckesr for LPDDR2 */
1104 tcksre = DIV_ROUND_UP(15000, clkper);
1105 tcksrx = tcksre;
1106 twr = DIV_ROUND_UP(15000, clkper) - 1;
1107 /*
1108 * tMRR: 2, tMRW: 5
1109 * tMRD should be set to max(tMRR, tMRW)
1110 */
1111 tmrd = 5;
1112 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
1113 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
1114 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
1115 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
1116 clkper / 10) - 1;
1117 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
1118 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
1119 /* To LPDDR2, CL in MDCFG0 refers to RL */
1120 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
1121 twtr = DIV_ROUND_UP(7500, clkper) - 1;
1122 trtp = DIV_ROUND_UP(7500, clkper) - 1;
1123
1124 cs0_end = 4 * sysinfo->cs_density - 1;
1125
1126 debug("density:%d Gb (%d Gb per chip)\n",
1127 sysinfo->cs_density, lpddr2_cfg->density);
1128 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1129 debug("memspd:%d\n", lpddr2_cfg->mem_speed);
1130 debug("trcd_lp=%d\n", trcd_lp);
1131 debug("trppb_lp=%d\n", trppb_lp);
1132 debug("trpab_lp=%d\n", trpab_lp);
1133 debug("trc_lp=%d\n", trc_lp);
1134 debug("tcke=%d\n", tcke);
1135 debug("tcksrx=%d\n", tcksrx);
1136 debug("tcksre=%d\n", tcksre);
1137 debug("trfc=%d\n", trfc);
1138 debug("txsr=%d\n", txsr);
1139 debug("txp=%d\n", txp);
1140 debug("tfaw=%d\n", tfaw);
1141 debug("tcl=%d\n", tcl);
1142 debug("tras=%d\n", tras);
1143 debug("twr=%d\n", twr);
1144 debug("tmrd=%d\n", tmrd);
1145 debug("twl=%d\n", twl);
1146 debug("trtp=%d\n", trtp);
1147 debug("twtr=%d\n", twtr);
1148 debug("trrd=%d\n", trrd);
1149 debug("cs0_end=%d\n", cs0_end);
1150 debug("ncs=%d\n", sysinfo->ncs);
1151
1152 /*
1153 * board-specific configuration:
1154 * These values are determined empirically and vary per board layout
1155 */
1156 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1157 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1158 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1159 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1160 mmdc0->mprddlctl = calib->p0_mprddlctl;
1161 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1162 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
1163
1164 /* Read data DQ Byte0-3 delay */
1165 mmdc0->mprddqby0dl = 0x33333333;
1166 mmdc0->mprddqby1dl = 0x33333333;
1167 if (sysinfo->dsize > 0) {
1168 mmdc0->mprddqby2dl = 0x33333333;
1169 mmdc0->mprddqby3dl = 0x33333333;
1170 }
1171
1172 /* Write data DQ Byte0-3 delay */
1173 mmdc0->mpwrdqby0dl = 0xf3333333;
1174 mmdc0->mpwrdqby1dl = 0xf3333333;
1175 if (sysinfo->dsize > 0) {
1176 mmdc0->mpwrdqby2dl = 0xf3333333;
1177 mmdc0->mpwrdqby3dl = 0xf3333333;
1178 }
1179
1180 /*
1181 * In LPDDR2 mode this register should be cleared,
1182 * so no termination will be activated.
1183 */
1184 mmdc0->mpodtctrl = 0;
1185
1186 /* complete calibration */
1187 val = (1 << 11); /* Force measurement on delay-lines */
1188 mmdc0->mpmur0 = val;
1189
1190 /* Step 1: configuration request */
1191 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1192
1193 /* Step 2: Timing configuration */
1194 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
1195 (tfaw << 4) | tcl;
1196 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
1197 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1198 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
1199 (trppb_lp << 4) | trpab_lp;
1200 mmdc0->mdotc = 0;
1201
1202 mmdc0->mdasp = cs0_end; /* CS addressing */
1203
1204 /* Step 3: Configure DDR type */
1205 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1206 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1207 (sysinfo->ralat << 6) | (1 << 3);
1208
1209 /* Step 4: Configure delay while leaving reset */
1210 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
1211 (sysinfo->rst_to_cke << 0);
1212
1213 /* Step 5: Configure DDR physical parameters (density and burst len) */
1214 coladdr = lpddr2_cfg->coladdr;
1215 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1216 coladdr += 4;
1217 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1218 coladdr += 1;
1219 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
1220 (coladdr - 9) << 20 | /* COL */
1221 (0 << 19) | /* Burst Length = 4 for LPDDR2 */
1222 (sysinfo->dsize << 16); /* DDR data bus size */
1223
1224 /* Step 6: Perform ZQ calibration */
1225 val = 0xa1390003; /* one-time HW ZQ calib */
1226 mmdc0->mpzqhwctrl = val;
1227
1228 /* Step 7: Enable MMDC with desired chip select */
1229 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1230 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1231
1232 /* Step 8: Write Mode Registers to Init LPDDR2 devices */
1233 for (cs = 0; cs < sysinfo->ncs; cs++) {
1234 /* MR63: reset */
1235 mmdc0->mdscr = MR(63, 0, 3, cs);
1236 /* MR10: calibration,
1237 * 0xff is calibration command after intilization.
1238 */
1239 val = 0xA | (0xff << 8);
1240 mmdc0->mdscr = MR(val, 0, 3, cs);
1241 /* MR1 */
1242 val = 0x1 | (0x82 << 8);
1243 mmdc0->mdscr = MR(val, 0, 3, cs);
1244 /* MR2 */
1245 val = 0x2 | (0x04 << 8);
1246 mmdc0->mdscr = MR(val, 0, 3, cs);
1247 /* MR3 */
1248 val = 0x3 | (0x02 << 8);
1249 mmdc0->mdscr = MR(val, 0, 3, cs);
1250 }
1251
1252 /* Step 10: Power down control and self-refresh */
1253 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1254 5 << 12 | /* PWDT_1: 256 cycles */
1255 5 << 8 | /* PWDT_0: 256 cycles */
1256 1 << 6 | /* BOTH_CS_PD */
1257 (tcksrx & 0x7) << 3 |
1258 (tcksre & 0x7);
1259 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1260
1261 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1262 val = 0xa1310003;
1263 mmdc0->mpzqhwctrl = val;
1264
1265 /* Step 12: Configure and activate periodic refresh */
1266 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1267
1268 /* Step 13: Deassert config request - init complete */
1269 mmdc0->mdscr = 0x00000000;
1270
1271 /* wait for auto-ZQ calibration to complete */
1272 mdelay(1);
1273 }
1274
mx6_ddr3_cfg(const struct mx6_ddr_sysinfo * sysinfo,const struct mx6_mmdc_calibration * calib,const struct mx6_ddr3_cfg * ddr3_cfg)1275 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1276 const struct mx6_mmdc_calibration *calib,
1277 const struct mx6_ddr3_cfg *ddr3_cfg)
1278 {
1279 volatile struct mmdc_p_regs *mmdc0;
1280 volatile struct mmdc_p_regs *mmdc1;
1281 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
1282 u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
1283 u32 val;
1284 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
1285 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
1286 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
1287 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
1288 u16 cs0_end;
1289 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
1290 u8 coladdr;
1291 int clkper; /* clock period in picoseconds */
1292 int clock; /* clock freq in MHz */
1293 int cs;
1294 u16 mem_speed = ddr3_cfg->mem_speed;
1295
1296 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1297 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
1298 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1299
1300 /* Limit mem_speed for MX6D/MX6Q */
1301 if (is_mx6dq() || is_mx6dqp()) {
1302 if (mem_speed > 1066)
1303 mem_speed = 1066; /* 1066 MT/s */
1304
1305 tcwl = 4;
1306 }
1307 /* Limit mem_speed for MX6S/MX6DL */
1308 else {
1309 if (mem_speed > 800)
1310 mem_speed = 800; /* 800 MT/s */
1311
1312 tcwl = 3;
1313 }
1314
1315 clock = mem_speed / 2;
1316 /*
1317 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
1318 * up to 528 MHz, so reduce the clock to fit chip specs
1319 */
1320 if (is_mx6dq() || is_mx6dqp()) {
1321 if (clock > 528)
1322 clock = 528; /* 528 MHz */
1323 }
1324
1325 clkper = (1000 * 1000) / clock; /* pico seconds */
1326 todtlon = tcwl;
1327 taxpd = tcwl;
1328 tanpd = tcwl;
1329
1330 switch (ddr3_cfg->density) {
1331 case 1: /* 1Gb per chip */
1332 trfc = DIV_ROUND_UP(110000, clkper) - 1;
1333 txs = DIV_ROUND_UP(120000, clkper) - 1;
1334 break;
1335 case 2: /* 2Gb per chip */
1336 trfc = DIV_ROUND_UP(160000, clkper) - 1;
1337 txs = DIV_ROUND_UP(170000, clkper) - 1;
1338 break;
1339 case 4: /* 4Gb per chip */
1340 trfc = DIV_ROUND_UP(260000, clkper) - 1;
1341 txs = DIV_ROUND_UP(270000, clkper) - 1;
1342 break;
1343 case 8: /* 8Gb per chip */
1344 trfc = DIV_ROUND_UP(350000, clkper) - 1;
1345 txs = DIV_ROUND_UP(360000, clkper) - 1;
1346 break;
1347 default:
1348 /* invalid density */
1349 puts("invalid chip density\n");
1350 hang();
1351 break;
1352 }
1353 txpr = txs;
1354
1355 switch (mem_speed) {
1356 case 800:
1357 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1358 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1359 if (ddr3_cfg->pagesz == 1) {
1360 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
1361 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1362 } else {
1363 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1364 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1365 }
1366 break;
1367 case 1066:
1368 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1369 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
1370 if (ddr3_cfg->pagesz == 1) {
1371 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
1372 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
1373 } else {
1374 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1375 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1376 }
1377 break;
1378 default:
1379 puts("invalid memory speed\n");
1380 hang();
1381 break;
1382 }
1383 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
1384 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
1385 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
1386 tcksrx = tcksre;
1387 taofpd = taonpd;
1388 twr = DIV_ROUND_UP(15000, clkper) - 1;
1389 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
1390 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
1391 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
1392 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
1393 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
1394 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
1395 trcd = trp;
1396 trtp = twtr;
1397 cs0_end = 4 * sysinfo->cs_density - 1;
1398
1399 debug("density:%d Gb (%d Gb per chip)\n",
1400 sysinfo->cs_density, ddr3_cfg->density);
1401 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1402 debug("memspd:%d\n", mem_speed);
1403 debug("tcke=%d\n", tcke);
1404 debug("tcksrx=%d\n", tcksrx);
1405 debug("tcksre=%d\n", tcksre);
1406 debug("taofpd=%d\n", taofpd);
1407 debug("taonpd=%d\n", taonpd);
1408 debug("todtlon=%d\n", todtlon);
1409 debug("tanpd=%d\n", tanpd);
1410 debug("taxpd=%d\n", taxpd);
1411 debug("trfc=%d\n", trfc);
1412 debug("txs=%d\n", txs);
1413 debug("txp=%d\n", txp);
1414 debug("txpdll=%d\n", txpdll);
1415 debug("tfaw=%d\n", tfaw);
1416 debug("tcl=%d\n", tcl);
1417 debug("trcd=%d\n", trcd);
1418 debug("trp=%d\n", trp);
1419 debug("trc=%d\n", trc);
1420 debug("tras=%d\n", tras);
1421 debug("twr=%d\n", twr);
1422 debug("tmrd=%d\n", tmrd);
1423 debug("tcwl=%d\n", tcwl);
1424 debug("tdllk=%d\n", tdllk);
1425 debug("trtp=%d\n", trtp);
1426 debug("twtr=%d\n", twtr);
1427 debug("trrd=%d\n", trrd);
1428 debug("txpr=%d\n", txpr);
1429 debug("cs0_end=%d\n", cs0_end);
1430 debug("ncs=%d\n", sysinfo->ncs);
1431 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
1432 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
1433 debug("SRT=%d\n", ddr3_cfg->SRT);
1434 debug("twr=%d\n", twr);
1435
1436 /*
1437 * board-specific configuration:
1438 * These values are determined empirically and vary per board layout
1439 * see:
1440 * appnote, ddr3 spreadsheet
1441 */
1442 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1443 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1444 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1445 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1446 mmdc0->mprddlctl = calib->p0_mprddlctl;
1447 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1448 if (sysinfo->dsize > 1) {
1449 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
1450 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
1451 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
1452 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
1453 MMDC1(mprddlctl, calib->p1_mprddlctl);
1454 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
1455 }
1456
1457 /* Read data DQ Byte0-3 delay */
1458 mmdc0->mprddqby0dl = 0x33333333;
1459 mmdc0->mprddqby1dl = 0x33333333;
1460 if (sysinfo->dsize > 0) {
1461 mmdc0->mprddqby2dl = 0x33333333;
1462 mmdc0->mprddqby3dl = 0x33333333;
1463 }
1464
1465 if (sysinfo->dsize > 1) {
1466 MMDC1(mprddqby0dl, 0x33333333);
1467 MMDC1(mprddqby1dl, 0x33333333);
1468 MMDC1(mprddqby2dl, 0x33333333);
1469 MMDC1(mprddqby3dl, 0x33333333);
1470 }
1471
1472 /*
1473 * MMDC Termination: rtt_nom:2 RZQ/2(120ohm),
1474 * rtt_nom:1 RZQ/4(60ohm),
1475 * rtt_nom:0 Disabled
1476 */
1477 if (sysinfo->rtt_nom == 0)
1478 val = 0x00000000;
1479 else if (sysinfo->rtt_nom == 2)
1480 val = 0x00011117;
1481 else
1482 val = 0x00022227;
1483 mmdc0->mpodtctrl = val;
1484 if (sysinfo->dsize > 1)
1485 MMDC1(mpodtctrl, val);
1486
1487 /* complete calibration */
1488 val = (1 << 11); /* Force measurement on delay-lines */
1489 mmdc0->mpmur0 = val;
1490 if (sysinfo->dsize > 1)
1491 MMDC1(mpmur0, val);
1492
1493 /* Step 1: configuration request */
1494 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1495
1496 /* Step 2: Timing configuration */
1497 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
1498 (txpdll << 9) | (tfaw << 4) | tcl;
1499 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
1500 (tras << 16) | (1 << 15) /* trpa */ |
1501 (twr << 9) | (tmrd << 5) | tcwl;
1502 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
1503 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
1504 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
1505 mmdc0->mdasp = cs0_end; /* CS addressing */
1506
1507 /* Step 3: Configure DDR type */
1508 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1509 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1510 (sysinfo->ralat << 6);
1511
1512 /* Step 4: Configure delay while leaving reset */
1513 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
1514 (sysinfo->rst_to_cke << 0);
1515
1516 /* Step 5: Configure DDR physical parameters (density and burst len) */
1517 coladdr = ddr3_cfg->coladdr;
1518 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1519 coladdr += 4;
1520 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1521 coladdr += 1;
1522 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
1523 (coladdr - 9) << 20 | /* COL */
1524 (1 << 19) | /* Burst Length = 8 for DDR3 */
1525 (sysinfo->dsize << 16); /* DDR data bus size */
1526
1527 /* Step 6: Perform ZQ calibration */
1528 val = 0xa1390001; /* one-time HW ZQ calib */
1529 mmdc0->mpzqhwctrl = val;
1530 if (sysinfo->dsize > 1)
1531 MMDC1(mpzqhwctrl, val);
1532
1533 /* Step 7: Enable MMDC with desired chip select */
1534 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1535 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1536
1537 /* Step 8: Write Mode Registers to Init DDR3 devices */
1538 mdelay(1); /* Wait before issuing the first MRS command.
1539 * Minimum wait time is (tXPR + 500us),
1540 * with max tXPR value 360ns, and 500us wait required after
1541 * RESET_n is de-asserted.
1542 */
1543 for (cs = 0; cs < sysinfo->ncs; cs++) {
1544 /* MR2 */
1545 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
1546 ((tcwl - 3) & 3) << 3;
1547 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
1548 mmdc0->mdscr = MR(val, 2, 3, cs);
1549 /* MR3 */
1550 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
1551 mmdc0->mdscr = MR(0, 3, 3, cs);
1552 /* MR1 */
1553 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
1554 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
1555 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
1556 mmdc0->mdscr = MR(val, 1, 3, cs);
1557 /* MR0 */
1558 val = ((tcl - 1) << 4) | /* CAS */
1559 (1 << 8) | /* DLL Reset */
1560 ((twr - 3) << 9) | /* Write Recovery */
1561 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
1562 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
1563 mmdc0->mdscr = MR(val, 0, 3, cs);
1564 /* ZQ calibration */
1565 val = (1 << 10);
1566 mmdc0->mdscr = MR(val, 0, 4, cs);
1567 }
1568
1569 /* Step 10: Power down control and self-refresh */
1570 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1571 5 << 12 | /* PWDT_1: 256 cycles */
1572 5 << 8 | /* PWDT_0: 256 cycles */
1573 1 << 6 | /* BOTH_CS_PD */
1574 (tcksrx & 0x7) << 3 |
1575 (tcksre & 0x7);
1576 if (!sysinfo->pd_fast_exit)
1577 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
1578 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1579
1580 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1581 val = 0xa1390003;
1582 mmdc0->mpzqhwctrl = val;
1583 if (sysinfo->dsize > 1)
1584 MMDC1(mpzqhwctrl, val);
1585
1586 /* Step 12: Configure and activate periodic refresh */
1587 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1588
1589 /*
1590 * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
1591 * configure it and disable MMDC arbitration/reordering (see EB828)
1592 */
1593 if (is_mx6dqp() &&
1594 ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
1595 (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
1596 struct mx6dqp_noc_sched_regs *noc_sched =
1597 (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
1598
1599 /*
1600 * These values are fixed based on integration parameters and
1601 * should not be modified
1602 */
1603 noc_sched->rlat = 0x00000040;
1604 noc_sched->ipu1 = 0x00000020;
1605 noc_sched->ipu2 = 0x00000020;
1606
1607 noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
1608 (tfaw << NOC_FAW_PERIOD_SHIFT) |
1609 (trrd << NOC_RD_SHIFT);
1610 noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
1611 << NOC_BW_RATIO_SHIFT) |
1612 ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
1613 ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
1614 (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
1615 ((tcwl + twr + trp + trcd)
1616 << NOC_WR_TO_MISS_SHIFT) |
1617 ((trtp + trp + trcd - 4)
1618 << NOC_RD_TO_MISS_SHIFT) |
1619 (trc << NOC_ACT_TO_ACT_SHIFT);
1620
1621 if (sysinfo->dsize == 2) {
1622 if (ddr3_cfg->coladdr == 10) {
1623 if (ddr3_cfg->rowaddr == 15 &&
1624 sysinfo->ncs == 2)
1625 noc_sched->ddrconf = 4;
1626 else
1627 noc_sched->ddrconf = 0;
1628 } else if (ddr3_cfg->coladdr == 11) {
1629 noc_sched->ddrconf = 1;
1630 }
1631 } else {
1632 if (ddr3_cfg->coladdr == 9) {
1633 if (ddr3_cfg->rowaddr == 13)
1634 noc_sched->ddrconf = 2;
1635 else if (ddr3_cfg->rowaddr == 14)
1636 noc_sched->ddrconf = 15;
1637 } else if (ddr3_cfg->coladdr == 10) {
1638 if (ddr3_cfg->rowaddr == 14 &&
1639 sysinfo->ncs == 2)
1640 noc_sched->ddrconf = 14;
1641 else if (ddr3_cfg->rowaddr == 15 &&
1642 sysinfo->ncs == 2)
1643 noc_sched->ddrconf = 9;
1644 else
1645 noc_sched->ddrconf = 3;
1646 } else if (ddr3_cfg->coladdr == 11) {
1647 if (ddr3_cfg->rowaddr == 15 &&
1648 sysinfo->ncs == 2)
1649 noc_sched->ddrconf = 4;
1650 else
1651 noc_sched->ddrconf = 0;
1652 } else if (ddr3_cfg->coladdr == 12) {
1653 if (ddr3_cfg->rowaddr == 14)
1654 noc_sched->ddrconf = 1;
1655 }
1656 }
1657
1658 /* Disable MMDC arbitration/reordering */
1659 mmdc0->maarcr = 0x14420000;
1660 }
1661
1662 /* Step 13: Deassert config request - init complete */
1663 mmdc0->mdscr = 0x00000000;
1664
1665 /* wait for auto-ZQ calibration to complete */
1666 mdelay(1);
1667 }
1668
mmdc_read_calibration(struct mx6_ddr_sysinfo const * sysinfo,struct mx6_mmdc_calibration * calib)1669 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
1670 struct mx6_mmdc_calibration *calib)
1671 {
1672 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1673 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1674
1675 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
1676 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
1677 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
1678 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
1679 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
1680 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
1681
1682 if (sysinfo->dsize == 2) {
1683 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
1684 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
1685 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
1686 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
1687 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
1688 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
1689 }
1690 }
1691
mx6_dram_cfg(const struct mx6_ddr_sysinfo * sysinfo,const struct mx6_mmdc_calibration * calib,const void * ddr_cfg)1692 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1693 const struct mx6_mmdc_calibration *calib,
1694 const void *ddr_cfg)
1695 {
1696 if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
1697 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
1698 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
1699 mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
1700 } else {
1701 puts("Unsupported ddr type\n");
1702 hang();
1703 }
1704 }
1705