1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <asm/io.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/dma.h>
14 #include <asm/mach-imx/hab.h>
15 #include <asm/mach-imx/rdc-sema.h>
16 #include <asm/arch/imx-rdc.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/sys_proto.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/bootm.h>
21 #include <dm.h>
22 #include <env.h>
23 #include <imx_thermal.h>
24 #include <asm/setup.h>
25 #include <linux/delay.h>
26
27 #define IOMUXC_GPR1 0x4
28 #define BM_IOMUXC_GPR1_IRQ 0x1000
29
30 #define GPC_LPCR_A7_BSC 0x0
31 #define GPC_LPCR_M4 0x8
32 #define GPC_SLPCR 0x14
33 #define GPC_PGC_ACK_SEL_A7 0x24
34 #define GPC_IMR1_CORE0 0x30
35 #define GPC_IMR1_CORE1 0x40
36 #define GPC_IMR1_M4 0x50
37 #define GPC_PGC_CPU_MAPPING 0xec
38 #define GPC_PGC_C0_PUPSCR 0x804
39 #define GPC_PGC_SCU_TIMING 0x890
40 #define GPC_PGC_C1_PUPSCR 0x844
41
42 #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
43 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
44 #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
45 #define BM_SLPCR_EN_DSM 0x80000000
46 #define BM_SLPCR_RBC_EN 0x40000000
47 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
48 #define BM_SLPCR_VSTBY 0x4
49 #define BM_SLPCR_SBYOS 0x2
50 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
51 #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
52
53 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
54 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
55
56 #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
57
58 #if defined(CONFIG_IMX_THERMAL)
59 static const struct imx_thermal_plat imx7_thermal_plat = {
60 .regs = (void *)ANATOP_BASE_ADDR,
61 .fuse_bank = 3,
62 .fuse_word = 3,
63 };
64
65 U_BOOT_DRVINFO(imx7_thermal) = {
66 .name = "imx_thermal",
67 .plat = &imx7_thermal_plat,
68 };
69 #endif
70
71 #if CONFIG_IS_ENABLED(IMX_RDC)
72 /*
73 * In current design, if any peripheral was assigned to both A7 and M4,
74 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
75 * low power mode. So M4 sleep will cause some peripherals fail to work
76 * at A7 core side. At default, all resources are in domain 0 - 3.
77 *
78 * There are 26 peripherals impacted by this IC issue:
79 * SIM2(sim2/emvsim2)
80 * SIM1(sim1/emvsim1)
81 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
82 * SAI1/SAI2/SAI3
83 * WDOG1/WDOG2/WDOG3/WDOG4
84 * GPT1/GPT2/GPT3/GPT4
85 * PWM1/PWM2/PWM3/PWM4
86 * ENET1/ENET2
87 * Software Workaround:
88 * Here we setup some resources to domain 0 where M4 codes will move
89 * the M4 out of this domain. Then M4 is not able to access them any longer.
90 * This is a workaround for ic issue. So the peripherals are not shared
91 * by them. This way requires the uboot implemented the RDC driver and
92 * set the 26 IPs above to domain 0 only. M4 code will assign resource
93 * to its own domain, if it want to use the resource.
94 */
95 static rdc_peri_cfg_t const resources[] = {
96 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
97 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
98 (RDC_PER_UART1 | RDC_DOMAIN(0)),
99 (RDC_PER_UART2 | RDC_DOMAIN(0)),
100 (RDC_PER_UART3 | RDC_DOMAIN(0)),
101 (RDC_PER_UART4 | RDC_DOMAIN(0)),
102 (RDC_PER_UART5 | RDC_DOMAIN(0)),
103 (RDC_PER_UART6 | RDC_DOMAIN(0)),
104 (RDC_PER_UART7 | RDC_DOMAIN(0)),
105 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
106 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
107 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
108 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
109 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
110 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
111 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
112 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
113 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
114 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
115 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
116 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
117 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
118 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
119 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
120 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
121 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
122 };
123
isolate_resource(void)124 static void isolate_resource(void)
125 {
126 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
127 }
128 #endif
129
130 #if defined(CONFIG_IMX_HAB)
131 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
132 .bank = 1,
133 .word = 3,
134 };
135 #endif
136
is_mx7d(void)137 static bool is_mx7d(void)
138 {
139 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
140 struct fuse_bank *bank = &ocotp->bank[1];
141 struct fuse_bank1_regs *fuse =
142 (struct fuse_bank1_regs *)bank->fuse_regs;
143 int val;
144
145 val = readl(&fuse->tester4);
146 if (val & 1)
147 return false;
148 else
149 return true;
150 }
151
get_cpu_rev(void)152 u32 get_cpu_rev(void)
153 {
154 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
155 ANATOP_BASE_ADDR;
156 u32 reg = readl(&ccm_anatop->digprog);
157 u32 type = (reg >> 16) & 0xff;
158
159 if (!is_mx7d())
160 type = MXC_CPU_MX7S;
161
162 reg &= 0xff;
163 return (type << 12) | reg;
164 }
165
166 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)167 u32 __weak get_board_rev(void)
168 {
169 return get_cpu_rev();
170 }
171 #endif
172
imx_enet_mdio_fixup(void)173 static void imx_enet_mdio_fixup(void)
174 {
175 struct iomuxc_gpr_base_regs *gpr_regs =
176 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
177
178 /*
179 * The management data input/output (MDIO) requires open-drain,
180 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
181 * this feature. So to TO1.1, need to enable open drain by setting
182 * bits GPR0[8:7].
183 */
184
185 if (soc_rev() >= CHIP_REV_1_1) {
186 setbits_le32(&gpr_regs->gpr[0],
187 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
188 }
189 }
190
init_cpu_basic(void)191 static void init_cpu_basic(void)
192 {
193 imx_enet_mdio_fixup();
194
195 #ifdef CONFIG_APBH_DMA
196 /* Start APBH DMA */
197 mxs_dma_init();
198 #endif
199 }
200
201 #ifdef CONFIG_IMX_BOOTAUX
202 /*
203 * Table of mappings of physical mem regions in both
204 * Cortex-A7 and Cortex-M4 address spaces.
205 *
206 * For additional details check sections 2.1.2 and 2.1.3 in
207 * i.MX7Dual Applications Processor Reference Manual
208 *
209 */
210 const struct rproc_att hostmap[] = {
211 /* aux core , host core, size */
212 { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
213 { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
214 { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
215 { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
216 { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
217 { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
218 { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
219 { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
220 { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
221 { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
222 { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
223 { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
224 { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
225 { /* sentinel */ }
226 };
227
imx_bootaux_get_hostmap(void)228 const struct rproc_att *imx_bootaux_get_hostmap(void)
229 {
230 return hostmap;
231 }
232 #endif
233
234 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
235 /* enable all periherial can be accessed in nosec mode */
init_csu(void)236 static void init_csu(void)
237 {
238 int i = 0;
239
240 for (i = 0; i < CSU_NUM_REGS; i++)
241 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
242 }
243
imx_gpcv2_init(void)244 static void imx_gpcv2_init(void)
245 {
246 u32 val, i;
247
248 /*
249 * Force IOMUXC irq pending, so that the interrupt to GPC can be
250 * used to deassert dsm_request signal when the signal gets
251 * asserted unexpectedly.
252 */
253 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
254 val |= BM_IOMUXC_GPR1_IRQ;
255 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
256
257 /* Initially mask all interrupts */
258 for (i = 0; i < 4; i++) {
259 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
260 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
261 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
262 }
263
264 /* set SCU timing */
265 writel((0x59 << 10) | 0x5B | (0x2 << 20),
266 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
267
268 /* only external IRQs to wake up LPM and core 0/1 */
269 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
270 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
271 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
272
273 /* set C0 power up timming per design requirement */
274 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
275 val &= ~BM_GPC_PGC_CORE_PUPSCR;
276 val |= (0x1A << 7);
277 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
278
279 /* set C1 power up timming per design requirement */
280 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
281 val &= ~BM_GPC_PGC_CORE_PUPSCR;
282 val |= (0x1A << 7);
283 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
284
285 /* dummy ack for time slot by default */
286 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
287 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
288 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
289
290 /* mask M4 DSM trigger */
291 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
292 BM_LPCR_M4_MASK_DSM_TRIGGER,
293 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
294
295 /* set mega/fast mix in A7 domain */
296 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
297
298 /* DSM related settings */
299 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
300 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
301 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
302 BM_SLPCR_REG_BYPASS_COUNT);
303 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
304 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
305
306 /*
307 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
308 * due to hardware design requirement, which is
309 * ~61us, here we use 65us for safe
310 */
311 udelay(65);
312 }
313
arch_cpu_init(void)314 int arch_cpu_init(void)
315 {
316 init_aips();
317
318 init_csu();
319 /* Disable PDE bit of WMCR register */
320 imx_wdog_disable_powerdown();
321
322 init_cpu_basic();
323
324 #if CONFIG_IS_ENABLED(IMX_RDC)
325 isolate_resource();
326 #endif
327
328 init_snvs();
329
330 imx_gpcv2_init();
331
332 enable_ca7_smp();
333
334 return 0;
335 }
336 #else
arch_cpu_init(void)337 int arch_cpu_init(void)
338 {
339 init_cpu_basic();
340
341 return 0;
342 }
343 #endif
344
345 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)346 int arch_misc_init(void)
347 {
348 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
349 struct tag_serialnr serialnr;
350 char serial_string[0x20];
351
352 if (is_mx7d())
353 env_set("soc", "imx7d");
354 else
355 env_set("soc", "imx7s");
356
357 /* Set serial# standard environment variable based on OTP settings */
358 get_board_serial(&serialnr);
359 snprintf(serial_string, sizeof(serial_string), "0x%08x%08x",
360 serialnr.low, serialnr.high);
361 env_set("serial#", serial_string);
362 #endif
363
364 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
365 struct udevice *dev;
366 int ret;
367 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
368 if (ret)
369 printf("Failed to initialize caam_jr: %d\n", ret);
370 }
371
372 return 0;
373 }
374 #endif
375
376 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
377 /*
378 * OCOTP_TESTER
379 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
380 * OCOTP_TESTER describes a unique ID based on silicon wafer
381 * and die X/Y position
382 *
383 * OCOTOP_TESTER offset 0x410
384 * 31:0 fuse 0
385 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
386 *
387 * OCOTP_TESTER1 offset 0x420
388 * 31:24 fuse 1
389 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
390 * 23:16 fuse 1
391 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
392 * 15:11 fuse 1
393 * The wafer number of the wafer on which the device was fabricated/SJC
394 * CHALLENGE/ Unique ID
395 * 10:0 fuse 1
396 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
397 */
get_board_serial(struct tag_serialnr * serialnr)398 void get_board_serial(struct tag_serialnr *serialnr)
399 {
400 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
401 struct fuse_bank *bank = &ocotp->bank[0];
402 struct fuse_bank0_regs *fuse =
403 (struct fuse_bank0_regs *)bank->fuse_regs;
404
405 serialnr->low = fuse->tester0;
406 serialnr->high = fuse->tester1;
407 }
408 #endif
409
set_wdog_reset(struct wdog_regs * wdog)410 void set_wdog_reset(struct wdog_regs *wdog)
411 {
412 u32 reg = readw(&wdog->wcr);
413 /*
414 * Output WDOG_B signal to reset external pmic or POR_B decided by
415 * the board desgin. Without external reset, the peripherals/DDR/
416 * PMIC are not reset, that may cause system working abnormal.
417 */
418 reg = readw(&wdog->wcr);
419 reg |= 1 << 3;
420 /*
421 * WDZST bit is write-once only bit. Align this bit in kernel,
422 * otherwise kernel code will have no chance to set this bit.
423 */
424 reg |= 1 << 0;
425 writew(reg, &wdog->wcr);
426 }
427
s_init(void)428 void s_init(void)
429 {
430 /* clock configuration. */
431 clock_init();
432
433 return;
434 }
435
436 #ifndef CONFIG_SPL_BUILD
437 const struct boot_mode soc_boot_modes[] = {
438 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
439 {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
440 {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
441 {NULL, 0},
442 };
443
boot_mode_getprisec(void)444 int boot_mode_getprisec(void)
445 {
446 struct src *psrc = (struct src *)SRC_BASE_ADDR;
447
448 return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
449 }
450 #endif
451
reset_misc(void)452 void reset_misc(void)
453 {
454 #ifndef CONFIG_SPL_BUILD
455 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
456 lcdif_power_down();
457 #endif
458 #endif
459 }
460