1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K3: AM64 SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 #ifndef __ASM_ARCH_AM64_HARDWARE_H 8 #define __ASM_ARCH_AM64_HARDWARE_H 9 10 #include <config.h> 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 #define PADCFG_MMR1_BASE 0x000f0000 16 #define MCU_PADCFG_MMR1_BASE 0x04080000 17 #define WKUP_CTRL_MMR0_BASE 0x43000000 18 #define MCU_CTRL_MMR0_BASE 0x04500000 19 #define CTRL_MMR0_BASE 0x43000000 20 21 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 22 23 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 24 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 25 26 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380 27 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 28 29 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00 30 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 31 32 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000 33 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 34 35 /* After the cfg mask and shifts have been applied */ 36 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 37 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 38 39 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 40 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 41 42 #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 43 44 #define ROM_EXTENDED_BOOT_DATA_INFO 0x701beb00 45 46 /* Use Last 2K as Scratch pad */ 47 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 48 49 #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) 50 51 #define AM64X_DEV_RTI8 127 52 #define AM64X_DEV_RTI9 128 53 #define AM64X_DEV_R5FSS0_CORE0 121 54 #define AM64X_DEV_R5FSS0_CORE1 122 55 56 static const u32 put_device_ids[] = { 57 AM64X_DEV_RTI9, 58 AM64X_DEV_RTI8, 59 }; 60 61 static const u32 put_core_ids[] = { 62 AM64X_DEV_R5FSS0_CORE1, 63 AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */ 64 }; 65 66 #endif 67 68 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ 69