1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * J721E: SoC specific initialization
4 *
5 * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
6 * David Huang <d-huang@ti.com>
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/armv7_mpu.h>
14 #include <asm/arch/hardware.h>
15 #include "sysfw-loader.h"
16 #include "common.h"
17 #include <linux/soc/ti/ti_sci_protocol.h>
18 #include <dm.h>
19 #include <dm/uclass-internal.h>
20 #include <dm/pinctrl.h>
21 #include <dm/root.h>
22 #include <mmc.h>
23 #include <remoteproc.h>
24
25 struct fwl_data cbass_hc_cfg0_fwls[] = {
26 { "PCIE0_CFG", 2577, 7 },
27 { "EMMC8SS0_CFG", 2579, 4 },
28 { "USB3SS0_CORE", 2580, 4 },
29 { "USB3SS1_CORE", 2581, 1 },
30 }, cbass_hc2_fwls[] = {
31 { "PCIE0", 2547, 24 },
32 { "HC2_WIZ16B8M4CT2", 2552, 1 },
33 }, cbass_rc_cfg0_fwls[] = {
34 { "EMMCSD4SS0_CFG", 2400, 4 },
35 }, infra_cbass0_fwls[] = {
36 { "PSC0", 5, 1 },
37 { "PLL_CTRL0", 6, 1 },
38 { "PLL_MMR0", 8, 26 },
39 { "CTRL_MMR0", 9, 16 },
40 { "GPIO0", 16, 1 },
41 }, mcu_cbass0_fwls[] = {
42 { "MCU_R5FSS0_CORE0", 1024, 4 },
43 { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
44 { "MCU_R5FSS0_CORE1", 1028, 4 },
45 { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
46 { "MCU_FSS0_CFG", 1032, 12 },
47 { "MCU_FSS0_S1", 1033, 8 },
48 { "MCU_FSS0_S0", 1036, 8 },
49 { "MCU_PSROM49152X32", 1048, 1 },
50 { "MCU_MSRAM128KX64", 1050, 8 },
51 { "MCU_MSRAM128KX64_CFG", 1051, 1 },
52 { "MCU_TIMER0", 1056, 1 },
53 { "MCU_TIMER9", 1065, 1 },
54 { "MCU_USART0", 1120, 1 },
55 { "MCU_I2C0", 1152, 1 },
56 { "MCU_CTRL_MMR0", 1200, 8 },
57 { "MCU_PLL_MMR0", 1201, 3 },
58 { "MCU_CPSW0", 1220, 2 },
59 }, wkup_cbass0_fwls[] = {
60 { "WKUP_PSC0", 129, 1 },
61 { "WKUP_PLL_CTRL0", 130, 1 },
62 { "WKUP_CTRL_MMR0", 131, 16 },
63 { "WKUP_GPIO0", 132, 1 },
64 { "WKUP_I2C0", 144, 1 },
65 { "WKUP_USART0", 160, 1 },
66 }, navss_cbass0_fwls[] = {
67 { "NACSS_VIRT0", 6253, 1 },
68 };
69
ctrl_mmr_unlock(void)70 static void ctrl_mmr_unlock(void)
71 {
72 /* Unlock all WKUP_CTRL_MMR0 module registers */
73 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
74 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
75 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
76 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
77 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
78 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
79 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
80
81 /* Unlock all MCU_CTRL_MMR0 module registers */
82 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
83 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
84 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
85 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
86 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
87
88 /* Unlock all CTRL_MMR0 module registers */
89 mmr_unlock(CTRL_MMR0_BASE, 0);
90 mmr_unlock(CTRL_MMR0_BASE, 1);
91 mmr_unlock(CTRL_MMR0_BASE, 2);
92 mmr_unlock(CTRL_MMR0_BASE, 3);
93 mmr_unlock(CTRL_MMR0_BASE, 5);
94 mmr_unlock(CTRL_MMR0_BASE, 7);
95 }
96
k3_mmc_stop_clock(void)97 void k3_mmc_stop_clock(void)
98 {
99 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
100 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
101 struct mmc *mmc = find_mmc_device(0);
102
103 if (!mmc)
104 return;
105
106 mmc->saved_clock = mmc->clock;
107 mmc_set_clock(mmc, 0, true);
108 }
109 }
110 }
111
k3_mmc_restart_clock(void)112 void k3_mmc_restart_clock(void)
113 {
114 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
115 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
116 struct mmc *mmc = find_mmc_device(0);
117
118 if (!mmc)
119 return;
120
121 mmc_set_clock(mmc, mmc->saved_clock, false);
122 }
123 }
124 }
125
126 /*
127 * This uninitialized global variable would normal end up in the .bss section,
128 * but the .bss is cleared between writing and reading this variable, so move
129 * it to the .data section.
130 */
131 u32 bootindex __attribute__((section(".data")));
132 static struct rom_extended_boot_data bootdata __section(".data");
133
store_boot_info_from_rom(void)134 static void store_boot_info_from_rom(void)
135 {
136 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
137 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
138 sizeof(struct rom_extended_boot_data));
139 }
140
k3_spl_init(void)141 void k3_spl_init(void)
142 {
143 struct udevice *dev;
144 int ret;
145 /*
146 * Cannot delay this further as there is a chance that
147 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
148 */
149 store_boot_info_from_rom();
150
151 /* Make all control module registers accessible */
152 ctrl_mmr_unlock();
153
154 if (IS_ENABLED(CONFIG_CPU_V7R)) {
155 disable_linefill_optimization();
156 setup_k3_mpu_regions();
157 }
158
159 /* Init DM early */
160 spl_early_init();
161
162 /* Prepare console output */
163 preloader_console_init();
164
165 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
166 /*
167 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
168 * regardless of the result of pinctrl. Do this without probing the
169 * device, but instead by searching the device that would request the
170 * given sequence number if probed. The UART will be used by the system
171 * firmware (SYSFW) image for various purposes and SYSFW depends on us
172 * to initialize its pin settings.
173 */
174 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
175 if (!ret)
176 pinctrl_select_state(dev, "default");
177
178 /*
179 * Load, start up, and configure system controller firmware. Provide
180 * the U-Boot console init function to the SYSFW post-PM configuration
181 * callback hook, effectively switching on (or over) the console
182 * output.
183 */
184 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
185 k3_mmc_stop_clock, k3_mmc_restart_clock);
186
187 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
188 /*
189 * Force probe of clk_k3 driver here to ensure basic default clock
190 * configuration is always done for enabling PM services.
191 */
192 ret = uclass_get_device_by_driver(UCLASS_CLK,
193 DM_DRIVER_GET(ti_clk),
194 &dev);
195 if (ret)
196 panic("Failed to initialize clk-k3!\n");
197 }
198
199 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
200 remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
201 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
202 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
203 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
204 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
205 remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
206 }
207
208 /* Output System Firmware version info */
209 k3_sysfw_print_ver();
210 }
211
check_rom_loaded_sysfw(void)212 bool check_rom_loaded_sysfw(void)
213 {
214 return is_rom_loaded_sysfw(&bootdata);
215 }
216
k3_mem_init(void)217 void k3_mem_init(void)
218 {
219 struct udevice *dev;
220 int ret;
221
222 if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
223 ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
224 if (ret)
225 panic("Probe of msmc failed: %d\n", ret);
226
227 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
228 if (ret)
229 panic("DRAM 0 init failed: %d\n", ret);
230
231 ret = uclass_next_device_err(&dev);
232 if (ret)
233 panic("DRAM 1 init failed: %d\n", ret);
234 }
235 spl_enable_dcache();
236 }
237
238 /* Support for the various EVM / SK families */
239 #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
do_dt_magic(void)240 void do_dt_magic(void)
241 {
242 int ret, rescan, mmc_dev = -1;
243 static struct mmc *mmc;
244
245 do_board_detect();
246
247 /*
248 * Board detection has been done.
249 * Let us see if another dtb wouldn't be a better match
250 * for our board
251 */
252 if (IS_ENABLED(CONFIG_CPU_V7R)) {
253 ret = fdtdec_resetup(&rescan);
254 if (!ret && rescan) {
255 dm_uninit();
256 dm_init_and_scan(true);
257 }
258 }
259
260 /*
261 * Because of multi DTB configuration, the MMC device has
262 * to be re-initialized after reconfiguring FDT inorder to
263 * boot from MMC. Do this when boot mode is MMC and ROM has
264 * not loaded SYSFW.
265 */
266 switch (spl_boot_device()) {
267 case BOOT_DEVICE_MMC1:
268 mmc_dev = 0;
269 break;
270 case BOOT_DEVICE_MMC2:
271 case BOOT_DEVICE_MMC2_2:
272 mmc_dev = 1;
273 break;
274 }
275
276 if (mmc_dev > 0 && !check_rom_loaded_sysfw()) {
277 ret = mmc_init_device(mmc_dev);
278 if (!ret) {
279 mmc = find_mmc_device(mmc_dev);
280 if (mmc) {
281 ret = mmc_init(mmc);
282 if (ret)
283 printf("mmc init failed with error: %d\n", ret);
284 }
285 }
286 }
287 }
288 #endif
289
290 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)291 void board_init_f(ulong dummy)
292 {
293 k3_spl_init();
294 #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT)
295 do_dt_magic();
296 #endif
297 k3_mem_init();
298 }
299 #endif
300
spl_mmc_boot_mode(struct mmc * mmc,const u32 boot_device)301 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
302 {
303 switch (boot_device) {
304 case BOOT_DEVICE_MMC1:
305 return MMCSD_MODE_EMMCBOOT;
306 case BOOT_DEVICE_MMC2:
307 return MMCSD_MODE_FS;
308 default:
309 return MMCSD_MODE_RAW;
310 }
311 }
312
__get_backup_bootmedia(u32 main_devstat)313 static u32 __get_backup_bootmedia(u32 main_devstat)
314 {
315 u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
316 MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
317
318 switch (bkup_boot) {
319 case BACKUP_BOOT_DEVICE_USB:
320 return BOOT_DEVICE_DFU;
321 case BACKUP_BOOT_DEVICE_UART:
322 return BOOT_DEVICE_UART;
323 case BACKUP_BOOT_DEVICE_ETHERNET:
324 return BOOT_DEVICE_ETHERNET;
325 case BACKUP_BOOT_DEVICE_MMC2:
326 {
327 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
328 MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
329 if (port == 0x0)
330 return BOOT_DEVICE_MMC1;
331 return BOOT_DEVICE_MMC2;
332 }
333 case BACKUP_BOOT_DEVICE_SPI:
334 return BOOT_DEVICE_SPI;
335 case BACKUP_BOOT_DEVICE_I2C:
336 return BOOT_DEVICE_I2C;
337 }
338
339 return BOOT_DEVICE_RAM;
340 }
341
__get_primary_bootmedia(u32 main_devstat,u32 wkup_devstat)342 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
343 {
344 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
345 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
346
347 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
348 BOOT_MODE_B_SHIFT;
349
350 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
351 bootmode == BOOT_DEVICE_XSPI)
352 bootmode = BOOT_DEVICE_SPI;
353
354 if (bootmode == BOOT_DEVICE_MMC2) {
355 u32 port = (main_devstat &
356 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
357 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
358 if (port == 0x0)
359 bootmode = BOOT_DEVICE_MMC1;
360 }
361
362 return bootmode;
363 }
364
spl_boot_device(void)365 u32 spl_boot_device(void)
366 {
367 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
368 u32 main_devstat;
369
370 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
371 printf("ERROR: MCU only boot is not yet supported\n");
372 return BOOT_DEVICE_RAM;
373 }
374
375 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
376 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
377
378 if (bootindex == K3_PRIMARY_BOOTMODE)
379 return __get_primary_bootmedia(main_devstat, wkup_devstat);
380 else
381 return __get_backup_bootmedia(main_devstat);
382 }
383