1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <ns16550.h>
9
10 #include <asm/arch/clk.h>
11 #include <asm/arch/uart.h>
12 #include <asm/arch/mux.h>
13 #include <asm/io.h>
14
15 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
16 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
17 static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
18
lpc32xx_uart_init(unsigned int uart_id)19 void lpc32xx_uart_init(unsigned int uart_id)
20 {
21 if (uart_id < 1 || uart_id > 7)
22 return;
23
24 /* Disable loopback mode, if it is set by S1L bootloader */
25 clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
26
27 if (uart_id < 3 || uart_id > 6)
28 return;
29
30 /* Enable UART system clock */
31 setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
32
33 /* Set UART into autoclock mode */
34 clrsetbits_le32(&ctrl->clkmode,
35 UART_CLKMODE_MASK(uart_id),
36 UART_CLKMODE_AUTO(uart_id));
37
38 /* Bypass pre-divider of UART clock */
39 writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
40 &clk->u3clk + (uart_id - 3));
41 }
42
43 #if !CONFIG_IS_ENABLED(OF_CONTROL)
44 static const struct ns16550_plat lpc32xx_uart[] = {
45 { .base = UART3_BASE, .reg_shift = 2,
46 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
47 { .base = UART4_BASE, .reg_shift = 2,
48 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
49 { .base = UART5_BASE, .reg_shift = 2,
50 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
51 { .base = UART6_BASE, .reg_shift = 2,
52 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
53 };
54
55 U_BOOT_DRVINFOS(lpc32xx_uarts) = {
56 { "ns16550_serial", &lpc32xx_uart[0], },
57 { "ns16550_serial", &lpc32xx_uart[1], },
58 { "ns16550_serial", &lpc32xx_uart[2], },
59 { "ns16550_serial", &lpc32xx_uart[3], },
60 };
61 #endif
62
lpc32xx_dma_init(void)63 void lpc32xx_dma_init(void)
64 {
65 /* Enable DMA interface */
66 writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
67 }
68
lpc32xx_mac_init(void)69 void lpc32xx_mac_init(void)
70 {
71 /* Enable MAC interface */
72 writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
73 #if defined(CONFIG_RMII)
74 | CLK_MAC_RMII,
75 #else
76 | CLK_MAC_MII,
77 #endif
78 &clk->macclk_ctrl);
79 }
80
lpc32xx_mlc_nand_init(void)81 void lpc32xx_mlc_nand_init(void)
82 {
83 /* Enable NAND interface */
84 writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
85 }
86
lpc32xx_slc_nand_init(void)87 void lpc32xx_slc_nand_init(void)
88 {
89 /* Enable SLC NAND interface */
90 writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
91 }
92
lpc32xx_usb_init(void)93 void lpc32xx_usb_init(void)
94 {
95 /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
96 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
97 }
98
lpc32xx_i2c_init(unsigned int devnum)99 void lpc32xx_i2c_init(unsigned int devnum)
100 {
101 /* Enable I2C interface */
102 uint32_t ctrl = readl(&clk->i2cclk_ctrl);
103 if (devnum == 1)
104 ctrl |= CLK_I2C1_ENABLE;
105 if (devnum == 2)
106 ctrl |= CLK_I2C2_ENABLE;
107 writel(ctrl, &clk->i2cclk_ctrl);
108 }
109
110 U_BOOT_DRVINFO(lpc32xx_gpios) = {
111 .name = "gpio_lpc32xx"
112 };
113
114 /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
115
116 #define P_MUX_SET_SSP0 0x1600
117
lpc32xx_ssp_init(void)118 void lpc32xx_ssp_init(void)
119 {
120 /* Enable SSP0 interface */
121 writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
122 /* Mux SSP0 pins */
123 writel(P_MUX_SET_SSP0, &mux->p_mux_set);
124 }
125