1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Configuration for MediaTek MT8512 SoC
4 *
5 * Copyright (C) 2019 MediaTek Inc.
6 * Author: Mingming Lee <mingming.lee@mediatek.com>
7 */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <init.h>
14 #include <log.h>
15 #include <ram.h>
16 #include <wdt.h>
17 #include <asm/arch/misc.h>
18 #include <asm/armv8/mmu.h>
19 #include <asm/cache.h>
20 #include <asm/global_data.h>
21 #include <asm/sections.h>
22 #include <dm/uclass.h>
23 #include <dt-bindings/clock/mt8512-clk.h>
24 #include <linux/sizes.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
dram_init(void)28 int dram_init(void)
29 {
30 return fdtdec_setup_mem_size_base();
31 }
32
get_effective_memsize(void)33 phys_size_t get_effective_memsize(void)
34 {
35 /* limit stack below tee reserve memory */
36 return gd->ram_size - 6 * SZ_1M;
37 }
38
dram_init_banksize(void)39 int dram_init_banksize(void)
40 {
41 gd->bd->bi_dram[0].start = gd->ram_base;
42 gd->bd->bi_dram[0].size = get_effective_memsize();
43
44 return 0;
45 }
46
reset_cpu(void)47 void reset_cpu(void)
48 {
49 struct udevice *watchdog_dev = NULL;
50
51 if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
52 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
53 psci_system_reset();
54
55 wdt_expire_now(watchdog_dev, 0);
56 }
57
print_cpuinfo(void)58 int print_cpuinfo(void)
59 {
60 debug("CPU: MediaTek MT8512\n");
61 return 0;
62 }
63
64 static struct mm_region mt8512_mem_map[] = {
65 {
66 /* DDR */
67 .virt = 0x40000000UL,
68 .phys = 0x40000000UL,
69 .size = 0x40000000UL,
70 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
71 }, {
72 .virt = 0x00000000UL,
73 .phys = 0x00000000UL,
74 .size = 0x40000000UL,
75 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
76 PTE_BLOCK_NON_SHARE |
77 PTE_BLOCK_PXN | PTE_BLOCK_UXN
78 }, {
79 0,
80 }
81 };
82
83 struct mm_region *mem_map = mt8512_mem_map;
84