1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <log.h>
10 #include <net.h>
11 #include <asm/arch/boot.h>
12 #include <asm/arch/eth.h>
13 #include <asm/arch/g12a.h>
14 #include <asm/arch/mem.h>
15 #include <asm/arch/meson-vpu.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/armv8/mmu.h>
19 #include <linux/sizes.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
meson_get_boot_device(void)23 int meson_get_boot_device(void)
24 {
25 return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
26 }
27
28 /* Configure the reserved memory zones exported by the secure registers
29 * into EFI and DTB reserved memory entries.
30 */
meson_init_reserved_memory(void * fdt)31 void meson_init_reserved_memory(void *fdt)
32 {
33 u64 bl31_size, bl31_start;
34 u64 bl32_size, bl32_start;
35 u32 reg;
36
37 /*
38 * Get ARM Trusted Firmware reserved memory zones in :
39 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
40 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
41 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
42 */
43 reg = readl(G12A_AO_SEC_GP_CFG3);
44
45 bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
46 >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
47 bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
48
49 bl31_start = readl(G12A_AO_SEC_GP_CFG5);
50 bl32_start = readl(G12A_AO_SEC_GP_CFG4);
51
52 /* Add BL31 reserved zone */
53 if (bl31_start && bl31_size)
54 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
55
56 /* Add BL32 reserved zone */
57 if (bl32_start && bl32_size)
58 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
59
60 #if defined(CONFIG_VIDEO_MESON)
61 meson_vpu_rsv_fb(fdt);
62 #endif
63 }
64
get_effective_memsize(void)65 phys_size_t get_effective_memsize(void)
66 {
67 /* Size is reported in MiB, convert it in bytes */
68 return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
69 >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
70 }
71
72 static struct mm_region g12a_mem_map[] = {
73 {
74 .virt = 0x0UL,
75 .phys = 0x0UL,
76 .size = 0xf5000000UL,
77 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
78 PTE_BLOCK_INNER_SHARE
79 }, {
80 .virt = 0xf5000000UL,
81 .phys = 0xf5000000UL,
82 .size = 0x0b000000UL,
83 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
84 PTE_BLOCK_NON_SHARE |
85 PTE_BLOCK_PXN | PTE_BLOCK_UXN
86 }, {
87 /* List terminator */
88 0,
89 }
90 };
91
92 struct mm_region *mem_map = g12a_mem_map;
93