1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Marvell International Ltd.
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <linux/libfdt.h>
10 #include <asm/io.h>
11 #include <asm/system.h>
12 #include <asm/arch/cpu.h>
13 #include <linux/sizes.h>
14 #include <asm/armv8/mmu.h>
15 #include "soc.h"
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define RAM_SIZE SZ_1G
20
21 static struct mm_region ac5_mem_map[] = {
22 {
23 /* RAM */
24 .phys = CFG_SYS_SDRAM_BASE,
25 .virt = CFG_SYS_SDRAM_BASE,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
27 PTE_BLOCK_INNER_SHARE
28 },
29 {
30 /* MMIO regions */
31 .phys = 0x00000000,
32 .virt = 0xa0000000,
33 .size = 0x100000,
34
35 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_NON_SHARE |
37 PTE_BLOCK_PXN | PTE_BLOCK_UXN
38 },
39 {
40 /* MMIO regions */
41 .phys = 0x100000,
42 .virt = 0x100000,
43 .size = 0x3ff00000,
44
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 },
49 {
50 /* MMIO regions */
51 .phys = 0x7F000000,
52 .virt = 0x7F000000,
53 .size = 0x21000000,
54
55 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56 PTE_BLOCK_NON_SHARE |
57 PTE_BLOCK_PXN | PTE_BLOCK_UXN
58 },
59 {
60 0,
61 }
62 };
63
64 struct mm_region *mem_map = ac5_mem_map;
65
reset_cpu(void)66 void reset_cpu(void)
67 {
68 }
69
print_cpuinfo(void)70 int print_cpuinfo(void)
71 {
72 soc_print_device_info();
73 soc_print_clock_info();
74
75 return 0;
76 }
77
alleycat5_dram_init(void)78 int alleycat5_dram_init(void)
79 {
80 #define SCRATCH_PAD_REG 0x80010018
81 int ret;
82
83 /* override DDR_FW size if DTS is set with size */
84 ret = fdtdec_setup_mem_size_base();
85 if (ret == -EINVAL)
86 gd->ram_size = readl(SCRATCH_PAD_REG) * 4ULL;
87
88 /* if DRAM size == 0, print error message */
89 if (gd->ram_size == 0) {
90 pr_err("DRAM size not initialized - check DRAM configuration\n");
91 printf("\n Using temporary DRAM size of 512MB.\n\n");
92 gd->ram_size = SZ_512M;
93 }
94
95 ac5_mem_map[0].size = gd->ram_size;
96
97 return 0;
98 }
99
alleycat5_dram_init_banksize(void)100 int alleycat5_dram_init_banksize(void)
101 {
102 /*
103 * Config single DRAM bank
104 */
105 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
106 gd->bd->bi_dram[0].size = gd->ram_size;
107
108 return 0;
109 }
110
timer_init(void)111 int timer_init(void)
112 {
113 return 0;
114 }
115
116 /*
117 * get_ref_clk
118 *
119 * return: reference clock in MHz
120 */
get_ref_clk(void)121 u32 get_ref_clk(void)
122 {
123 return 25;
124 }
125