1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <init.h>
10 #include <asm/cache.h>
11 #include <asm/global_data.h>
12 #include <asm/ptrace.h>
13 #include <linux/libfdt.h>
14 #include <linux/sizes.h>
15 #include <pci.h>
16 #include <asm/io.h>
17 #include <asm/system.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/armv8/mmu.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 /*
25  * Not all memory is mapped in the MMU. So we need to restrict the
26  * memory size so that U-Boot does not try to access it. Also, the
27  * internal registers are located at 0xf000.0000 - 0xffff.ffff.
28  * Currently only 2GiB are mapped for system memory. This is what
29  * we pass to the U-Boot subsystem here.
30  */
31 #define USABLE_RAM_SIZE		0x80000000ULL
32 
board_get_usable_ram_top(phys_size_t total_size)33 phys_size_t board_get_usable_ram_top(phys_size_t total_size)
34 {
35 	unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
36 
37 	return (gd->ram_top > top) ? top : gd->ram_top;
38 }
39 
40 /*
41  * On ARMv8, MBus is not configured in U-Boot. To enable compilation
42  * of the already implemented drivers, lets add a dummy version of
43  * this function so that linking does not fail.
44  */
mvebu_mbus_dram_info(void)45 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
46 {
47 	return NULL;
48 }
49 
dram_init_banksize(void)50 __weak int dram_init_banksize(void)
51 {
52 	if (IS_ENABLED(CONFIG_ARMADA_8K))
53 		return a8k_dram_init_banksize();
54 	else if (IS_ENABLED(CONFIG_ARMADA_3700))
55 		return a3700_dram_init_banksize();
56 	else if (IS_ENABLED(CONFIG_ALLEYCAT_5))
57 		return alleycat5_dram_init_banksize();
58 	else
59 		return fdtdec_setup_memory_banksize();
60 }
61 
dram_init(void)62 __weak int dram_init(void)
63 {
64 	if (IS_ENABLED(CONFIG_ARMADA_8K)) {
65 		gd->ram_size = a8k_dram_scan_ap_sz();
66 		if (gd->ram_size != 0)
67 			return 0;
68 	}
69 
70 	if (IS_ENABLED(CONFIG_ARMADA_3700))
71 		return a3700_dram_init();
72 
73 	if (IS_ENABLED(CONFIG_ALLEYCAT_5))
74 		return alleycat5_dram_init();
75 
76 	if (fdtdec_setup_mem_size_base() != 0)
77 		return -EINVAL;
78 
79 	return 0;
80 }
81 
arch_cpu_init(void)82 int arch_cpu_init(void)
83 {
84 	/* Nothing to do (yet) */
85 	return 0;
86 }
87 
arch_early_init_r(void)88 int arch_early_init_r(void)
89 {
90 	struct udevice *dev;
91 	int ret;
92 	int i;
93 
94 	/*
95 	 * Loop over all MISC uclass drivers to call the comphy code
96 	 * and init all CP110 devices enabled in the DT
97 	 */
98 	i = 0;
99 	while (1) {
100 		/* Call the comphy code via the MISC uclass driver */
101 		ret = uclass_get_device(UCLASS_MISC, i++, &dev);
102 
103 		/* We're done, once no further CP110 device is found */
104 		if (ret)
105 			break;
106 	}
107 
108 	/* Cause the SATA device to do its early init */
109 	uclass_first_device(UCLASS_AHCI, &dev);
110 
111 	/* Trigger PCIe devices detection */
112 	if (IS_ENABLED(CONFIG_PCI))
113 		pci_init();
114 
115 	return 0;
116 }
117