1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <linux/libfdt.h>
11 #include <linux/sizes.h>
12 #include <asm/io.h>
13 #include <asm/system.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/soc.h>
16 #include <asm/armv8/mmu.h>
17 #include <mach/fw_info.h>
18
19 /* Armada 7k/8k */
20 #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
21 #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
22 #define RFU_SW_RESET_OFFSET 0
23
24 #define SAR0_REG (MVEBU_REGISTER(0x2400200))
25 #define BOOT_MODE_MASK 0x3f
26 #define BOOT_MODE_OFFSET 4
27
28 static struct mm_region mvebu_mem_map[] = {
29 /* Armada 80x0 memory regions include the CP1 (slave) units */
30 {
31 /* RAM 0-64MB */
32 .phys = 0x0UL,
33 .virt = 0x0UL,
34 .size = ATF_REGION_START,
35 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
36 PTE_BLOCK_INNER_SHARE
37 },
38 /* ATF and TEE region 0x4000000-0x5400000 not mapped */
39 {
40 /* RAM 66MB-2GB */
41 .phys = ATF_REGION_END,
42 .virt = ATF_REGION_END,
43 .size = SZ_2G,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 PTE_BLOCK_INNER_SHARE
46 },
47 {
48 /* MMIO regions */
49 .phys = MMIO_REGS_PHY_BASE,
50 .virt = MMIO_REGS_PHY_BASE,
51 .size = SZ_1G,
52
53 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
54 PTE_BLOCK_NON_SHARE
55 },
56 {
57 0,
58 }
59 };
60
61 struct mm_region *mem_map = mvebu_mem_map;
62
enable_caches(void)63 void enable_caches(void)
64 {
65 icache_enable();
66 dcache_enable();
67 }
68
reset_cpu(void)69 void reset_cpu(void)
70 {
71 u32 reg;
72
73 reg = readl(RFU_GLOBAL_SW_RST);
74 reg &= ~(1 << RFU_SW_RESET_OFFSET);
75 writel(reg, RFU_GLOBAL_SW_RST);
76 }
77
78 /*
79 * TODO - implement this functionality using platform
80 * clock driver once it gets available
81 * Return NAND clock in Hz
82 */
mvebu_get_nand_clock(void)83 u32 mvebu_get_nand_clock(void)
84 {
85 unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
86 unsigned long NF_CLOCK_SEL_MASK = 0x1;
87 u32 reg;
88
89 reg = readl(NAND_FLASH_CLK_CTRL);
90 if (reg & NF_CLOCK_SEL_MASK)
91 return 400 * 1000000;
92 else
93 return 250 * 1000000;
94 }
95
mmc_get_env_dev(void)96 int mmc_get_env_dev(void)
97 {
98 u32 reg;
99 unsigned int boot_mode;
100
101 reg = readl(SAR0_REG);
102 boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK;
103
104 switch (boot_mode) {
105 case 0x28:
106 case 0x2a:
107 return 0;
108 case 0x29:
109 case 0x2b:
110 return 1;
111 }
112
113 return CONFIG_SYS_MMC_ENV_DEV;
114 }
115