1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Common board functions for AM33XX based boards
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <debug_uart.h>
13 #include <errno.h>
14 #include <event.h>
15 #include <init.h>
16 #include <net.h>
17 #include <ns16550.h>
18 #include <omap3_spi.h>
19 #include <spl.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/i2c.h>
27 #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
28 #include <asm/arch/mem-guardian.h>
29 #else
30 #include <asm/arch/mem.h>
31 #endif
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/global_data.h>
35 #include <asm/io.h>
36 #include <asm/emif.h>
37 #include <asm/gpio.h>
38 #include <asm/omap_common.h>
39 #include <i2c.h>
40 #include <miiphy.h>
41 #include <cpsw.h>
42 #include <linux/delay.h>
43 #include <linux/errno.h>
44 #include <linux/compiler.h>
45 #include <linux/usb/ch9.h>
46 #include <linux/usb/gadget.h>
47 #include <linux/usb/musb.h>
48 #include <asm/omap_musb.h>
49 #include <asm/davinci_rtc.h>
50
51 #define AM43XX_EMIF_BASE 0x4C000000
52 #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
53 #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
54 #define AM43XX_SDRAM_TYPE_SHIFT 29
55 #define AM43XX_SDRAM_TYPE_DDR3 3
56 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
57 #define AM43XX_RDWRLVLFULL_START 0x80000000
58
59 /* SPI flash. */
60 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
61 #define AM33XX_SPI0_BASE 0x48030000
62 #define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
63 #endif
64
65 DECLARE_GLOBAL_DATA_PTR;
66
dram_init(void)67 int dram_init(void)
68 {
69 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
70 sdram_init();
71 #endif
72
73 /* dram_init must store complete ramsize in gd->ram_size */
74 gd->ram_size = get_ram_size(
75 (void *)CFG_SYS_SDRAM_BASE,
76 CFG_MAX_RAM_BANK_SIZE);
77 return 0;
78 }
79
dram_init_banksize(void)80 int dram_init_banksize(void)
81 {
82 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
83 gd->bd->bi_dram[0].size = gd->ram_size;
84
85 return 0;
86 }
87
88 #if !CONFIG_IS_ENABLED(OF_CONTROL)
89 static const struct ns16550_plat am33xx_serial[] = {
90 { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
91 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
92 # ifdef CFG_SYS_NS16550_COM2
93 { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
94 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
95 # ifdef CFG_SYS_NS16550_COM3
96 { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
97 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
98 { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
99 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
100 { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
101 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
102 { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
103 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
104 # endif
105 # endif
106 };
107
108 U_BOOT_DRVINFOS(am33xx_uarts) = {
109 { "ns16550_serial", &am33xx_serial[0] },
110 # ifdef CFG_SYS_NS16550_COM2
111 { "ns16550_serial", &am33xx_serial[1] },
112 # ifdef CFG_SYS_NS16550_COM3
113 { "ns16550_serial", &am33xx_serial[2] },
114 { "ns16550_serial", &am33xx_serial[3] },
115 { "ns16550_serial", &am33xx_serial[4] },
116 { "ns16550_serial", &am33xx_serial[5] },
117 # endif
118 # endif
119 };
120
121 #if CONFIG_IS_ENABLED(DM_I2C)
122 static const struct omap_i2c_plat am33xx_i2c[] = {
123 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
124 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
125 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
126 };
127
128 U_BOOT_DRVINFOS(am33xx_i2c) = {
129 { "i2c_omap", &am33xx_i2c[0] },
130 { "i2c_omap", &am33xx_i2c[1] },
131 { "i2c_omap", &am33xx_i2c[2] },
132 };
133 #endif
134
135 #if CONFIG_IS_ENABLED(DM_GPIO)
136 static const struct omap_gpio_plat am33xx_gpio[] = {
137 { 0, AM33XX_GPIO0_BASE },
138 { 1, AM33XX_GPIO1_BASE },
139 { 2, AM33XX_GPIO2_BASE },
140 { 3, AM33XX_GPIO3_BASE },
141 #ifdef CONFIG_AM43XX
142 { 4, AM33XX_GPIO4_BASE },
143 { 5, AM33XX_GPIO5_BASE },
144 #endif
145 };
146
147 U_BOOT_DRVINFOS(am33xx_gpios) = {
148 { "gpio_omap", &am33xx_gpio[0] },
149 { "gpio_omap", &am33xx_gpio[1] },
150 { "gpio_omap", &am33xx_gpio[2] },
151 { "gpio_omap", &am33xx_gpio[3] },
152 #ifdef CONFIG_AM43XX
153 { "gpio_omap", &am33xx_gpio[4] },
154 { "gpio_omap", &am33xx_gpio[5] },
155 #endif
156 };
157 #endif
158 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
159 static const struct omap3_spi_plat omap3_spi_pdata = {
160 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
161 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
162 };
163
164 U_BOOT_DRVINFO(am33xx_spi) = {
165 .name = "omap3_spi",
166 .plat = &omap3_spi_pdata,
167 };
168 #endif
169 #endif
170
171 #if !CONFIG_IS_ENABLED(DM_GPIO)
172 static const struct gpio_bank gpio_bank_am33xx[] = {
173 { (void *)AM33XX_GPIO0_BASE },
174 { (void *)AM33XX_GPIO1_BASE },
175 { (void *)AM33XX_GPIO2_BASE },
176 { (void *)AM33XX_GPIO3_BASE },
177 #ifdef CONFIG_AM43XX
178 { (void *)AM33XX_GPIO4_BASE },
179 { (void *)AM33XX_GPIO5_BASE },
180 #endif
181 };
182
183 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
184 #endif
185
186 #if defined(CONFIG_MMC_OMAP_HS)
cpu_mmc_init(struct bd_info * bis)187 int cpu_mmc_init(struct bd_info *bis)
188 {
189 int ret;
190
191 ret = omap_mmc_init(0, 0, 0, -1, -1);
192 if (ret)
193 return ret;
194
195 return omap_mmc_init(1, 0, 0, -1, -1);
196 }
197 #endif
198
199 /*
200 * RTC only with DDR in self-refresh mode magic value, checked against during
201 * boot to see if we have a valid config. This should be in sync with the value
202 * that will be in drivers/soc/ti/pm33xx.c.
203 */
204 #define RTC_MAGIC_VAL 0x8cd0
205
206 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
207 #define RTC_BOARD_TYPE_SHIFT 16
208
209 /* AM33XX has two MUSB controllers which can be host or gadget */
210 #if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
211 defined(CONFIG_SPL_BUILD)
212
213 static struct musb_hdrc_config musb_config = {
214 .multipoint = 1,
215 .dyn_fifo = 1,
216 .num_eps = 16,
217 .ram_bits = 12,
218 };
219
220 #ifdef CONFIG_AM335X_USB0
221 static struct ti_musb_plat usb0 = {
222 .base = (void *)USB0_OTG_BASE,
223 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
224 .plat = {
225 .config = &musb_config,
226 .power = 50,
227 .platform_ops = &musb_dsps_ops,
228 },
229 };
230 #endif
231
232 #ifdef CONFIG_AM335X_USB1
233 static struct ti_musb_plat usb1 = {
234 .base = (void *)USB1_OTG_BASE,
235 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
236 .plat = {
237 .config = &musb_config,
238 .power = 50,
239 .platform_ops = &musb_dsps_ops,
240 },
241 };
242 #endif
243
244 U_BOOT_DRVINFOS(am33xx_usbs) = {
245 #ifdef CONFIG_AM335X_USB0_PERIPHERAL
246 { "ti-musb-peripheral", &usb0 },
247 #elif defined(CONFIG_AM335X_USB0_HOST)
248 { "ti-musb-host", &usb0 },
249 #endif
250 #ifdef CONFIG_AM335X_USB1_PERIPHERAL
251 { "ti-musb-peripheral", &usb1 },
252 #elif defined(CONFIG_AM335X_USB1_HOST)
253 { "ti-musb-host", &usb1 },
254 #endif
255 };
256
arch_misc_init(void)257 int arch_misc_init(void)
258 {
259 return 0;
260 }
261 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
262
arch_misc_init(void)263 int arch_misc_init(void)
264 {
265 struct udevice *dev;
266 int ret;
267
268 ret = uclass_first_device_err(UCLASS_MISC, &dev);
269 if (ret)
270 return ret;
271
272 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
273 ret = usb_ether_init();
274 if (ret) {
275 pr_err("USB ether init failed\n");
276 return ret;
277 }
278 #endif
279
280 return 0;
281 }
282
283 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
284
285 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
286
287 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
288 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
rtc32k_unlock(struct davinci_rtc * rtc)289 static void rtc32k_unlock(struct davinci_rtc *rtc)
290 {
291 /*
292 * Unlock the RTC's registers. For more details please see the
293 * RTC_SS section of the TRM. In order to unlock we need to
294 * write these specific values (keys) in this order.
295 */
296 writel(RTC_KICK0R_WE, &rtc->kick0r);
297 writel(RTC_KICK1R_WE, &rtc->kick1r);
298 }
299 #endif
300
301 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
302 /*
303 * Write contents of the RTC_SCRATCH1 register based on board type
304 * Two things are passed
305 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
306 * control gets to kernel, kernel reads the scratchpad register and gets to
307 * know that bootloader has rtc_only support.
308 *
309 * Second important thing is the board type (16:31). This is needed in the
310 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
311 * identify the board type and we go ahead and copy the board strings to
312 * am43xx_board_name.
313 */
update_rtc_magic(void)314 void update_rtc_magic(void)
315 {
316 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
317 u32 magic = RTC_MAGIC_VAL;
318
319 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
320
321 rtc32k_unlock(rtc);
322
323 /* write magic */
324 writel(magic, &rtc->scratch1);
325 }
326 #endif
327
328 /*
329 * In the case of non-SPL based booting we'll want to call these
330 * functions a tiny bit later as it will require gd to be set and cleared
331 * and that's not true in s_init in this case so we cannot do it there.
332 */
board_early_init_f(void)333 int board_early_init_f(void)
334 {
335 set_mux_conf_regs();
336 prcm_init();
337 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
338 update_rtc_magic();
339 #endif
340 return 0;
341 }
342
343 /*
344 * This function is the place to do per-board things such as ramp up the
345 * MPU clock frequency.
346 */
am33xx_spl_board_init(void)347 __weak void am33xx_spl_board_init(void)
348 {
349 }
350
351 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
rtc32k_enable(void)352 static void rtc32k_enable(void)
353 {
354 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
355
356 rtc32k_unlock(rtc);
357
358 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
359 writel((1 << 3) | (1 << 6), &rtc->osc);
360 }
361 #endif
362
uart_soft_reset(void)363 static void uart_soft_reset(void)
364 {
365 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
366 u32 regval;
367
368 regval = readl(&uart_base->uartsyscfg);
369 regval |= UART_RESET;
370 writel(regval, &uart_base->uartsyscfg);
371 while ((readl(&uart_base->uartsyssts) &
372 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
373 ;
374
375 /* Disable smart idle */
376 regval = readl(&uart_base->uartsyscfg);
377 regval |= UART_SMART_IDLE_EN;
378 writel(regval, &uart_base->uartsyscfg);
379 }
380
watchdog_disable(void)381 static void watchdog_disable(void)
382 {
383 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
384
385 writel(0xAAAA, &wdtimer->wdtwspr);
386 while (readl(&wdtimer->wdtwwps) != 0x0)
387 ;
388 writel(0x5555, &wdtimer->wdtwspr);
389 while (readl(&wdtimer->wdtwwps) != 0x0)
390 ;
391 }
392
393 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
394 /*
395 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
396 */
rtc_only(void)397 static void rtc_only(void)
398 {
399 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
400 struct prm_device_inst *prm_device =
401 (struct prm_device_inst *)PRM_DEVICE_INST;
402
403 u32 scratch1, sdrc;
404 void (*resume_func)(void);
405
406 scratch1 = readl(&rtc->scratch1);
407
408 /*
409 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
410 * written to this register when we want to wake up from RTC only
411 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
412 * bits 0-15: RTC_MAGIC_VAL
413 * bits 16-31: board type (needed for sdram_init)
414 */
415 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
416 return;
417
418 rtc32k_unlock(rtc);
419
420 /* Clear RTC magic */
421 writel(0, &rtc->scratch1);
422
423 /*
424 * Update board type based on value stored on RTC_SCRATCH1, this
425 * is done so that we don't need to read the board type from eeprom
426 * over i2c bus which is expensive
427 */
428 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
429
430 /*
431 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
432 * are resuming from self-refresh. This avoids an unnecessary re-init
433 * of the DDR. The re-init takes time and we would need to wait for
434 * it to complete before accessing DDR to avoid L3 NOC errors.
435 */
436 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
437
438 rtc_only_prcm_init();
439 sdram_init();
440
441 /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
442 /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
443 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
444
445 sdrc &= AM43XX_SDRAM_TYPE_MASK;
446 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
447
448 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
449 writel(AM43XX_RDWRLVLFULL_START,
450 AM43XX_EMIF_BASE +
451 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
452 mdelay(1);
453
454 am43xx_wait:
455 sdrc = readl(AM43XX_EMIF_BASE +
456 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
457 if (sdrc == AM43XX_RDWRLVLFULL_START)
458 goto am43xx_wait;
459 }
460
461 resume_func = (void *)readl(&rtc->scratch0);
462 if (resume_func)
463 resume_func();
464 }
465 #endif
466
s_init(void)467 void s_init(void)
468 {
469 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
470 rtc_only();
471 #endif
472 }
473
early_system_init(void)474 void early_system_init(void)
475 {
476 /*
477 * The ROM will only have set up sufficient pinmux to allow for the
478 * first 4KiB NOR to be read, we must finish doing what we know of
479 * the NOR mux in this space in order to continue.
480 */
481 #ifdef CONFIG_NOR_BOOT
482 enable_norboot_pin_mux();
483 #endif
484 watchdog_disable();
485 set_uart_mux_conf();
486 setup_early_clocks();
487 uart_soft_reset();
488 #ifdef CONFIG_SPL_BUILD
489 /*
490 * Save the boot parameters passed from romcode.
491 * We cannot delay the saving further than this,
492 * to prevent overwrites.
493 */
494 save_omap_boot_params();
495 #endif
496 #ifdef CONFIG_DEBUG_UART_OMAP
497 debug_uart_init();
498 #endif
499
500 #ifdef CONFIG_SPL_BUILD
501 spl_early_init();
502 #endif
503
504 #ifdef CONFIG_TI_I2C_BOARD_DETECT
505 do_board_detect();
506 #endif
507
508 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
509 /* Enable RTC32K clock */
510 rtc32k_enable();
511 #endif
512 }
513
514 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)515 void board_init_f(ulong dummy)
516 {
517 hw_data_init();
518 early_system_init();
519 board_early_init_f();
520 sdram_init();
521 /* dram_init must store complete ramsize in gd->ram_size */
522 gd->ram_size = get_ram_size(
523 (void *)CFG_SYS_SDRAM_BASE,
524 CFG_MAX_RAM_BANK_SIZE);
525 }
526 #endif
527
528 #endif
529
am33xx_dm_post_init(void * ctx,struct event * event)530 static int am33xx_dm_post_init(void *ctx, struct event *event)
531 {
532 hw_data_init();
533 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
534 early_system_init();
535 #endif
536 return 0;
537 }
538 EVENT_SPY(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
539