1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <fdt_support.h>
8 #include <init.h>
9 #include <log.h>
10 #include <spl.h>
11 #include <spl_gpio.h>
12 #include <syscon.h>
13 #include <asm/armv8/mmu.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch-rockchip/bootrom.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/cru.h>
19 #include <asm/arch-rockchip/gpio.h>
20 #include <asm/arch-rockchip/grf_rk3399.h>
21 #include <asm/arch-rockchip/hardware.h>
22 #include <linux/bitops.h>
23 #include <power/regulator.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define GRF_EMMCCORE_CON11 0xff77f02c
28 #define GRF_BASE 0xff770000
29
30 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
31 [BROM_BOOTSOURCE_EMMC] = "/mmc@fe330000",
32 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000/flash@0",
33 [BROM_BOOTSOURCE_SD] = "/mmc@fe320000",
34 };
35
36 static struct mm_region rk3399_mem_map[] = {
37 {
38 .virt = 0x0UL,
39 .phys = 0x0UL,
40 .size = 0xf8000000UL,
41 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
42 PTE_BLOCK_INNER_SHARE
43 }, {
44 .virt = 0xf8000000UL,
45 .phys = 0xf8000000UL,
46 .size = 0x08000000UL,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48 PTE_BLOCK_NON_SHARE |
49 PTE_BLOCK_PXN | PTE_BLOCK_UXN
50 }, {
51 /* List terminator */
52 0,
53 }
54 };
55
56 struct mm_region *mem_map = rk3399_mem_map;
57
58 #ifdef CONFIG_SPL_BUILD
59
60 #define TIMER_END_COUNT_L 0x00
61 #define TIMER_END_COUNT_H 0x04
62 #define TIMER_INIT_COUNT_L 0x10
63 #define TIMER_INIT_COUNT_H 0x14
64 #define TIMER_CONTROL_REG 0x1c
65
66 #define TIMER_EN 0x1
67 #define TIMER_FMODE BIT(0)
68 #define TIMER_RMODE BIT(1)
69
rockchip_stimer_init(void)70 void rockchip_stimer_init(void)
71 {
72 /* If Timer already enabled, don't re-init it */
73 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
74
75 if (reg & TIMER_EN)
76 return;
77
78 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
79 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
80 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
81 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
82 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
83 TIMER_CONTROL_REG);
84 }
85 #endif
86
arch_cpu_init(void)87 int arch_cpu_init(void)
88 {
89
90 #ifdef CONFIG_SPL_BUILD
91 struct rk3399_pmusgrf_regs *sgrf;
92 struct rk3399_grf_regs *grf;
93
94 /*
95 * Disable DDR and SRAM security regions.
96 *
97 * As we are entered from the BootROM, the region from
98 * 0x0 through 0xfffff (i.e. the first MB of memory) will
99 * be protected. This will cause issues with the DW_MMC
100 * driver, which tries to DMA from/to the stack (likely)
101 * located in this range.
102 */
103 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
104 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
105 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
106
107 /* eMMC clock generator: disable the clock multipilier */
108 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
109 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
110 #endif
111
112 return 0;
113 }
114
115 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)116 void board_debug_uart_init(void)
117 {
118 #define GRF_BASE 0xff770000
119 #define GPIO0_BASE 0xff720000
120 #define PMUGRF_BASE 0xff320000
121 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
122
123 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
124 /* Enable early UART0 on the RK3399 */
125 rk_clrsetreg(&grf->gpio2c_iomux,
126 GRF_GPIO2C0_SEL_MASK,
127 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
128 rk_clrsetreg(&grf->gpio2c_iomux,
129 GRF_GPIO2C1_SEL_MASK,
130 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
131 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
132 /* Enable early UART3 on the RK3399 */
133 rk_clrsetreg(&grf->gpio3b_iomux,
134 GRF_GPIO3B6_SEL_MASK,
135 GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
136 rk_clrsetreg(&grf->gpio3b_iomux,
137 GRF_GPIO3B7_SEL_MASK,
138 GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
139 #else
140 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
141 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
142
143 if (IS_ENABLED(CONFIG_SPL_BUILD) &&
144 (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
145 IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
146 rk_setreg(&grf->io_vsel, 1 << 0);
147
148 /*
149 * Let's enable these power rails here, we are already running
150 * the SPI-Flash-based code.
151 */
152 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
153 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2),
154 GPIO_PULL_NORMAL);
155
156 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
157 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4),
158 GPIO_PULL_NORMAL);
159 }
160
161 /* Enable early UART2 channel C on the RK3399 */
162 rk_clrsetreg(&grf->gpio4c_iomux,
163 GRF_GPIO4C3_SEL_MASK,
164 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
165 rk_clrsetreg(&grf->gpio4c_iomux,
166 GRF_GPIO4C4_SEL_MASK,
167 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
168 /* Set channel C as UART2 input */
169 rk_clrsetreg(&grf->soc_con7,
170 GRF_UART_DBG_SEL_MASK,
171 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
172 #endif
173 }
174 #endif
175
176 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
spl_decode_boot_device(u32 boot_device)177 const char *spl_decode_boot_device(u32 boot_device)
178 {
179 int i;
180 static const struct {
181 u32 boot_device;
182 const char *ofpath;
183 } spl_boot_devices_tbl[] = {
184 { BOOT_DEVICE_MMC2, "/mmc@fe320000" },
185 { BOOT_DEVICE_MMC1, "/mmc@fe330000" },
186 { BOOT_DEVICE_SPI, "/spi@ff1d0000/flash@0" },
187 };
188
189 for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
190 if (spl_boot_devices_tbl[i].boot_device == boot_device)
191 return spl_boot_devices_tbl[i].ofpath;
192
193 return NULL;
194 }
195
spl_perform_fixups(struct spl_image_info * spl_image)196 void spl_perform_fixups(struct spl_image_info *spl_image)
197 {
198 void *blob = spl_image->fdt_addr;
199 const char *boot_ofpath;
200 int chosen;
201
202 /*
203 * Inject the ofpath of the device the full U-Boot (or Linux in
204 * Falcon-mode) was booted from into the FDT, if a FDT has been
205 * loaded at the same time.
206 */
207 if (!blob)
208 return;
209
210 boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
211 if (!boot_ofpath) {
212 pr_err("%s: could not map boot_device to ofpath\n", __func__);
213 return;
214 }
215
216 chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
217 if (chosen < 0) {
218 pr_err("%s: could not find/create '/chosen'\n", __func__);
219 return;
220 }
221 fdt_setprop_string(blob, chosen,
222 "u-boot,spl-boot-device", boot_ofpath);
223 }
224
rk3399_force_power_on_reset(void)225 static void rk3399_force_power_on_reset(void)
226 {
227 ofnode node;
228 struct gpio_desc sysreset_gpio;
229
230 if (!IS_ENABLED(CONFIG_SPL_GPIO)) {
231 debug("%s: trying to force a power-on reset but no GPIO "
232 "support in SPL!\n", __func__);
233 return;
234 }
235
236 debug("%s: trying to force a power-on reset\n", __func__);
237
238 node = ofnode_path("/config");
239 if (!ofnode_valid(node)) {
240 debug("%s: no /config node?\n", __func__);
241 return;
242 }
243
244 if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
245 &sysreset_gpio, GPIOD_IS_OUT)) {
246 debug("%s: could not find a /config/sysreset-gpio\n", __func__);
247 return;
248 }
249
250 dm_gpio_set_value(&sysreset_gpio, 1);
251 }
252
led_setup(void)253 void __weak led_setup(void)
254 {
255 }
256
spl_board_init(void)257 void spl_board_init(void)
258 {
259 led_setup();
260
261 if (IS_ENABLED(CONFIG_SPL_GPIO)) {
262 struct rockchip_cru *cru = rockchip_get_cru();
263
264 /*
265 * The RK3399 resets only 'almost all logic' (see also in the
266 * TRM "3.9.4 Global software reset"), when issuing a software
267 * reset. This may cause issues during boot-up for some
268 * configurations of the application software stack.
269 *
270 * To work around this, we test whether the last reset reason
271 * was a power-on reset and (if not) issue an overtemp-reset to
272 * reset the entire module.
273 *
274 * While this was previously fixed by modifying the various
275 * places that could generate a software reset (e.g. U-Boot's
276 * sysreset driver, the ATF or Linux), we now have it here to
277 * ensure that we no longer have to track this through the
278 * various components.
279 */
280 if (cru->glb_rst_st != 0)
281 rk3399_force_power_on_reset();
282 }
283
284 if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) {
285 /*
286 * Turning the eMMC and SPI back on (if disabled via the Qseven
287 * BIOS_ENABLE) signal is done through a always-on regulator).
288 */
289 if (regulators_enable_boot_on(false))
290 debug("%s: Cannot enable boot on regulator\n",
291 __func__);
292 }
293 }
294 #endif
295