1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Clock drivers for Qualcomm QCS404
4 *
5 * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6 */
7
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <asm/io.h>
13 #include <linux/bitops.h>
14 #include "clock-snapdragon.h"
15
16 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
17
18 /* GPLL0 clock control registers */
19 #define GPLL0_STATUS_ACTIVE BIT(31)
20
21 #define CFG_CLK_SRC_GPLL1 BIT(8)
22 #define GPLL1_STATUS_ACTIVE BIT(31)
23
24 static struct vote_clk gcc_blsp1_ahb_clk = {
25 .cbcr_reg = BLSP1_AHB_CBCR,
26 .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
27 .vote_bit = BIT(10) | BIT(5) | BIT(4),
28 };
29
30 static const struct bcr_regs uart2_regs = {
31 .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
32 .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
33 .M = BLSP1_UART2_APPS_M,
34 .N = BLSP1_UART2_APPS_N,
35 .D = BLSP1_UART2_APPS_D,
36 };
37
38 static const struct bcr_regs sdc_regs = {
39 .cfg_rcgr = SDCC_CFG_RCGR(1),
40 .cmd_rcgr = SDCC_CMD_RCGR(1),
41 .M = SDCC_M(1),
42 .N = SDCC_N(1),
43 .D = SDCC_D(1),
44 };
45
46 static struct pll_vote_clk gpll0_vote_clk = {
47 .status = GPLL0_STATUS,
48 .status_bit = GPLL0_STATUS_ACTIVE,
49 .ena_vote = APCS_GPLL_ENA_VOTE,
50 .vote_bit = BIT(0),
51 };
52
53 static struct pll_vote_clk gpll1_vote_clk = {
54 .status = GPLL1_STATUS,
55 .status_bit = GPLL1_STATUS_ACTIVE,
56 .ena_vote = APCS_GPLL_ENA_VOTE,
57 .vote_bit = BIT(1),
58 };
59
60 static const struct bcr_regs usb30_master_regs = {
61 .cfg_rcgr = USB30_MASTER_CFG_RCGR,
62 .cmd_rcgr = USB30_MASTER_CMD_RCGR,
63 .M = USB30_MASTER_M,
64 .N = USB30_MASTER_N,
65 .D = USB30_MASTER_D,
66 };
67
68 static const struct bcr_regs emac_regs = {
69 .cfg_rcgr = EMAC_CFG_RCGR,
70 .cmd_rcgr = EMAC_CMD_RCGR,
71 .M = EMAC_M,
72 .N = EMAC_N,
73 .D = EMAC_D,
74 };
75
76 static const struct bcr_regs emac_ptp_regs = {
77 .cfg_rcgr = EMAC_PTP_CFG_RCGR,
78 .cmd_rcgr = EMAC_PTP_CMD_RCGR,
79 .M = EMAC_M,
80 .N = EMAC_N,
81 .D = EMAC_D,
82 };
83
84 static const struct bcr_regs blsp1_qup0_i2c_apps_regs = {
85 .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR,
86 .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR,
87 /* mnd_width = 0 */
88 };
89
90 static const struct bcr_regs blsp1_qup1_i2c_apps_regs = {
91 .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
92 .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR,
93 /* mnd_width = 0 */
94 };
95
96 static const struct bcr_regs blsp1_qup2_i2c_apps_regs = {
97 .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
98 .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR,
99 /* mnd_width = 0 */
100 };
101
102 static const struct bcr_regs blsp1_qup3_i2c_apps_regs = {
103 .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
104 .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR,
105 /* mnd_width = 0 */
106 };
107
108 static const struct bcr_regs blsp1_qup4_i2c_apps_regs = {
109 .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
110 .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR,
111 /* mnd_width = 0 */
112 };
113
msm_set_rate(struct clk * clk,ulong rate)114 ulong msm_set_rate(struct clk *clk, ulong rate)
115 {
116 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
117
118 switch (clk->id) {
119 case GCC_BLSP1_UART2_APPS_CLK:
120 /* UART: 115200 */
121 clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
122 CFG_CLK_SRC_CXO);
123 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
124 break;
125 case GCC_BLSP1_AHB_CLK:
126 clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
127 break;
128 case GCC_SDCC1_APPS_CLK:
129 /* SDCC1: 200MHz */
130 clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
131 CFG_CLK_SRC_GPLL0);
132 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
133 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
134 break;
135 case GCC_SDCC1_AHB_CLK:
136 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
137 break;
138 case GCC_ETH_RGMII_CLK:
139 if (rate == 250000000)
140 clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
141 CFG_CLK_SRC_GPLL1);
142 else if (rate == 125000000)
143 clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
144 CFG_CLK_SRC_GPLL1);
145 else if (rate == 50000000)
146 clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
147 CFG_CLK_SRC_GPLL1);
148 else if (rate == 5000000)
149 clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
150 CFG_CLK_SRC_GPLL1);
151 break;
152 default:
153 return 0;
154 }
155
156 return 0;
157 }
158
msm_enable(struct clk * clk)159 int msm_enable(struct clk *clk)
160 {
161 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
162
163 switch (clk->id) {
164 case GCC_USB30_MASTER_CLK:
165 clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
166 clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
167 CFG_CLK_SRC_GPLL0);
168 break;
169 case GCC_SYS_NOC_USB3_CLK:
170 clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
171 break;
172 case GCC_USB30_SLEEP_CLK:
173 clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
174 break;
175 case GCC_USB30_MOCK_UTMI_CLK:
176 clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
177 break;
178 case GCC_USB_HS_PHY_CFG_AHB_CLK:
179 clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
180 break;
181 case GCC_USB2A_PHY_SLEEP_CLK:
182 clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
183 break;
184 case GCC_ETH_PTP_CLK:
185 /* SPEED_1000: freq -> 250MHz */
186 clk_enable_cbc(priv->base + ETH_PTP_CBCR);
187 clk_enable_gpll0(priv->base, &gpll1_vote_clk);
188 clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
189 CFG_CLK_SRC_GPLL1);
190 break;
191 case GCC_ETH_RGMII_CLK:
192 /* SPEED_1000: freq -> 250MHz */
193 clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
194 clk_enable_gpll0(priv->base, &gpll1_vote_clk);
195 clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
196 CFG_CLK_SRC_GPLL1);
197 break;
198 case GCC_ETH_SLAVE_AHB_CLK:
199 clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
200 break;
201 case GCC_ETH_AXI_CLK:
202 clk_enable_cbc(priv->base + ETH_AXI_CBCR);
203 break;
204 case GCC_BLSP1_AHB_CLK:
205 clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
206 break;
207 case GCC_BLSP1_QUP0_I2C_APPS_CLK:
208 clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR);
209 clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0,
210 CFG_CLK_SRC_CXO);
211 break;
212 case GCC_BLSP1_QUP1_I2C_APPS_CLK:
213 clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
214 clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0,
215 CFG_CLK_SRC_CXO);
216 break;
217 case GCC_BLSP1_QUP2_I2C_APPS_CLK:
218 clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
219 clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0,
220 CFG_CLK_SRC_CXO);
221 break;
222 case GCC_BLSP1_QUP3_I2C_APPS_CLK:
223 clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR);
224 clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0,
225 CFG_CLK_SRC_CXO);
226 break;
227 case GCC_BLSP1_QUP4_I2C_APPS_CLK:
228 clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
229 clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
230 CFG_CLK_SRC_CXO);
231 break;
232 default:
233 return 0;
234 }
235
236 return 0;
237 }
238