1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Clock drivers for Qualcomm APQ8016, APQ8096
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * Based on Little Kernel driver, simplified
8 */
9
10 #include <common.h>
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <asm/io.h>
15 #include <linux/bitops.h>
16 #include "clock-snapdragon.h"
17
18 /* CBCR register fields */
19 #define CBCR_BRANCH_ENABLE_BIT BIT(0)
20 #define CBCR_BRANCH_OFF_BIT BIT(31)
21
22 extern ulong msm_set_rate(struct clk *clk, ulong rate);
23 extern int msm_enable(struct clk *clk);
24
25 /* Enable clock controlled by CBC soft macro */
clk_enable_cbc(phys_addr_t cbcr)26 void clk_enable_cbc(phys_addr_t cbcr)
27 {
28 setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
29
30 while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
31 ;
32 }
33
clk_enable_gpll0(phys_addr_t base,const struct pll_vote_clk * gpll0)34 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
35 {
36 if (readl(base + gpll0->status) & gpll0->status_bit)
37 return; /* clock already enabled */
38
39 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
40
41 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
42 ;
43 }
44
45 #define BRANCH_ON_VAL (0)
46 #define BRANCH_NOC_FSM_ON_VAL BIT(29)
47 #define BRANCH_CHECK_MASK GENMASK(31, 28)
48
clk_enable_vote_clk(phys_addr_t base,const struct vote_clk * vclk)49 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
50 {
51 u32 val;
52
53 setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
54 do {
55 val = readl(base + vclk->cbcr_reg);
56 val &= BRANCH_CHECK_MASK;
57 } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
58 }
59
60 #define APPS_CMD_RCGR_UPDATE BIT(0)
61
62 /* Update clock command via CMD_RCGR */
clk_bcr_update(phys_addr_t apps_cmd_rcgr)63 void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
64 {
65 setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
66
67 /* Wait for frequency to be updated. */
68 while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)
69 ;
70 }
71
72 #define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
73
74 #define CFG_MASK 0x3FFF
75
76 #define CFG_DIVIDER_MASK 0x1F
77
78 /* root set rate for clocks with half integer and MND divider */
clk_rcg_set_rate_mnd(phys_addr_t base,const struct bcr_regs * regs,int div,int m,int n,int source)79 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
80 int div, int m, int n, int source)
81 {
82 u32 cfg;
83 /* M value for MND divider. */
84 u32 m_val = m;
85 /* NOT(N-M) value for MND divider. */
86 u32 n_val = ~((n) - (m)) * !!(n);
87 /* NOT 2D value for MND divider. */
88 u32 d_val = ~(n);
89
90 /* Program MND values */
91 writel(m_val, base + regs->M);
92 writel(n_val, base + regs->N);
93 writel(d_val, base + regs->D);
94
95 /* setup src select and divider */
96 cfg = readl(base + regs->cfg_rcgr);
97 cfg &= ~CFG_MASK;
98 cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
99
100 /* Set the divider; HW permits fraction dividers (+0.5), but
101 for simplicity, we will support integers only */
102 if (div)
103 cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
104
105 if (n_val)
106 cfg |= CFG_MODE_DUAL_EDGE;
107
108 writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
109
110 /* Inform h/w to start using the new config. */
111 clk_bcr_update(base + regs->cmd_rcgr);
112 }
113
114 /* root set rate for clocks with half integer and mnd_width=0 */
clk_rcg_set_rate(phys_addr_t base,const struct bcr_regs * regs,int div,int source)115 void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
116 int source)
117 {
118 u32 cfg;
119
120 /* setup src select and divider */
121 cfg = readl(base + regs->cfg_rcgr);
122 cfg &= ~CFG_MASK;
123 cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
124
125 /*
126 * Set the divider; HW permits fraction dividers (+0.5), but
127 * for simplicity, we will support integers only
128 */
129 if (div)
130 cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
131
132 writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
133
134 /* Inform h/w to start using the new config. */
135 clk_bcr_update(base + regs->cmd_rcgr);
136 }
137
msm_clk_probe(struct udevice * dev)138 static int msm_clk_probe(struct udevice *dev)
139 {
140 struct msm_clk_priv *priv = dev_get_priv(dev);
141
142 priv->base = dev_read_addr(dev);
143 if (priv->base == FDT_ADDR_T_NONE)
144 return -EINVAL;
145
146 return 0;
147 }
148
msm_clk_set_rate(struct clk * clk,ulong rate)149 static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
150 {
151 return msm_set_rate(clk, rate);
152 }
153
msm_clk_enable(struct clk * clk)154 static int msm_clk_enable(struct clk *clk)
155 {
156 return msm_enable(clk);
157 }
158
159 static struct clk_ops msm_clk_ops = {
160 .set_rate = msm_clk_set_rate,
161 .enable = msm_clk_enable,
162 };
163
164 static const struct udevice_id msm_clk_ids[] = {
165 { .compatible = "qcom,gcc-msm8916" },
166 { .compatible = "qcom,gcc-apq8016" },
167 { .compatible = "qcom,gcc-msm8996" },
168 { .compatible = "qcom,gcc-apq8096" },
169 { .compatible = "qcom,gcc-sdm845" },
170 { .compatible = "qcom,gcc-qcs404" },
171 { }
172 };
173
174 U_BOOT_DRIVER(clk_msm) = {
175 .name = "clk_msm",
176 .id = UCLASS_CLK,
177 .of_match = msm_clk_ids,
178 .ops = &msm_clk_ops,
179 .priv_auto = sizeof(struct msm_clk_priv),
180 .probe = msm_clk_probe,
181 };
182