1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Qualcomm QCS404 sysmap
4  *
5  * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6  */
7 #ifndef _MACH_SYSMAP_QCS404_H
8 #define _MACH_SYSMAP_QCS404_H
9 
10 #define GICD_BASE			(0x0b000000)
11 #define GICC_BASE			(0x0b002000)
12 
13 /* Clocks: (from CLK_CTL_BASE)  */
14 #define GPLL0_STATUS			(0x21000)
15 #define GPLL1_STATUS			(0x20000)
16 #define APCS_GPLL_ENA_VOTE		(0x45000)
17 #define APCS_CLOCK_BRANCH_ENA_VOTE	(0x45004)
18 
19 /* BLSP1 AHB clock (root clock for BLSP) */
20 #define BLSP1_AHB_CBCR			0x1008
21 
22 /* Uart clock control registers */
23 #define BLSP1_UART2_BCR			(0x3028)
24 #define BLSP1_UART2_APPS_CBCR		(0x302C)
25 #define BLSP1_UART2_APPS_CMD_RCGR	(0x3034)
26 #define BLSP1_UART2_APPS_CFG_RCGR	(0x3038)
27 #define BLSP1_UART2_APPS_M		(0x303C)
28 #define BLSP1_UART2_APPS_N		(0x3040)
29 #define BLSP1_UART2_APPS_D		(0x3044)
30 
31 /* I2C controller clock control registerss */
32 #define BLSP1_QUP0_I2C_APPS_CBCR	(0x6028)
33 #define BLSP1_QUP0_I2C_APPS_CMD_RCGR	(0x602C)
34 #define BLSP1_QUP0_I2C_APPS_CFG_RCGR	(0x6030)
35 #define BLSP1_QUP1_I2C_APPS_CBCR	(0x2008)
36 #define BLSP1_QUP1_I2C_APPS_CMD_RCGR	(0x200C)
37 #define BLSP1_QUP1_I2C_APPS_CFG_RCGR	(0x2010)
38 #define BLSP1_QUP2_I2C_APPS_CBCR	(0x3010)
39 #define BLSP1_QUP2_I2C_APPS_CMD_RCGR	(0x3000)
40 #define BLSP1_QUP2_I2C_APPS_CFG_RCGR	(0x3004)
41 #define BLSP1_QUP3_I2C_APPS_CBCR	(0x4020)
42 #define BLSP1_QUP3_I2C_APPS_CMD_RCGR	(0x4000)
43 #define BLSP1_QUP3_I2C_APPS_CFG_RCGR	(0x4004)
44 #define BLSP1_QUP4_I2C_APPS_CBCR	(0x5020)
45 #define BLSP1_QUP4_I2C_APPS_CMD_RCGR	(0x5000)
46 #define BLSP1_QUP4_I2C_APPS_CFG_RCGR	(0x5004)
47 
48 /* SD controller clock control registers */
49 #define SDCC_BCR(n)			(((n) * 0x1000) + 0x41000)
50 #define SDCC_CMD_RCGR(n)		(((n) * 0x1000) + 0x41004)
51 #define SDCC_CFG_RCGR(n)		(((n) * 0x1000) + 0x41008)
52 #define SDCC_M(n)			(((n) * 0x1000) + 0x4100C)
53 #define SDCC_N(n)			(((n) * 0x1000) + 0x41010)
54 #define SDCC_D(n)			(((n) * 0x1000) + 0x41014)
55 #define SDCC_APPS_CBCR(n)		(((n) * 0x1000) + 0x41018)
56 #define SDCC_AHB_CBCR(n)		(((n) * 0x1000) + 0x4101C)
57 
58 /* USB-3.0 controller clock control registers */
59 #define SYS_NOC_USB3_CBCR		(0x26014)
60 #define USB30_BCR			(0x39000)
61 #define USB3PHY_BCR			(0x39008)
62 #define USB30_MASTER_CBCR		(0x3900C)
63 #define USB30_SLEEP_CBCR		(0x39010)
64 #define USB30_MOCK_UTMI_CBCR		(0x39014)
65 #define USB30_MOCK_UTMI_CMD_RCGR	(0x3901C)
66 #define USB30_MOCK_UTMI_CFG_RCGR	(0x39020)
67 #define USB30_MASTER_CMD_RCGR		(0x39028)
68 #define USB30_MASTER_CFG_RCGR		(0x3902C)
69 #define USB30_MASTER_M			(0x39030)
70 #define USB30_MASTER_N			(0x39034)
71 #define USB30_MASTER_D			(0x39038)
72 #define USB2A_PHY_SLEEP_CBCR		(0x4102C)
73 #define USB_HS_PHY_CFG_AHB_CBCR		(0x41030)
74 
75 /* ETH controller clock control registers */
76 #define ETH_PTP_CBCR			(0x4e004)
77 #define ETH_RGMII_CBCR			(0x4e008)
78 #define ETH_SLAVE_AHB_CBCR		(0x4e00c)
79 #define ETH_AXI_CBCR			(0x4e010)
80 #define EMAC_PTP_CMD_RCGR		(0x4e014)
81 #define EMAC_PTP_CFG_RCGR		(0x4e018)
82 #define EMAC_CMD_RCGR			(0x4e01c)
83 #define EMAC_CFG_RCGR			(0x4e020)
84 #define EMAC_M				(0x4e024)
85 #define EMAC_N				(0x4e028)
86 #define EMAC_D				(0x4e02c)
87 
88 #endif
89