1# SPDX-License-Identifier: GPL-2.0+
2#
3# (C) Copyright 2000-2003
4# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5#
6# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
7# Copyright (C) 2017-2021 Intel Corporation <www.intel.com>
8
9obj-y	+= board.o
10obj-y	+= clock_manager.o
11obj-y	+= misc.o
12
13ifdef CONFIG_TARGET_SOCFPGA_GEN5
14obj-y	+= clock_manager_gen5.o
15obj-y	+= misc_gen5.o
16obj-y	+= reset_manager_gen5.o
17obj-y	+= scan_manager.o
18obj-y	+= system_manager_gen5.o
19obj-y	+= timer.o
20obj-y	+= wrap_pll_config.o
21obj-y	+= fpga_manager.o
22endif
23
24ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
25obj-y	+= clock_manager_arria10.o
26obj-y	+= misc_arria10.o
27obj-y	+= pinmux_arria10.o
28obj-y	+= reset_manager_arria10.o
29endif
30
31ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
32obj-y	+= clock_manager_s10.o
33obj-y	+= lowlevel_init_soc64.o
34obj-y	+= mailbox_s10.o
35obj-y	+= misc_soc64.o
36obj-y	+= mmu-arm64_s10.o
37obj-y	+= reset_manager_s10.o
38obj-y	+= system_manager_soc64.o
39obj-y	+= timer_s10.o
40obj-y	+= wrap_handoff_soc64.o
41obj-y	+= wrap_pll_config_soc64.o
42endif
43
44ifdef CONFIG_TARGET_SOCFPGA_AGILEX
45obj-y	+= clock_manager_agilex.o
46obj-y	+= lowlevel_init_soc64.o
47obj-y	+= mailbox_s10.o
48obj-y	+= misc_soc64.o
49obj-y	+= mmu-arm64_s10.o
50obj-y	+= reset_manager_s10.o
51obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= secure_vab.o
52obj-y	+= system_manager_soc64.o
53obj-y	+= timer_s10.o
54obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= vab.o
55obj-y	+= wrap_handoff_soc64.o
56obj-y	+= wrap_pll_config_soc64.o
57endif
58
59ifdef CONFIG_TARGET_SOCFPGA_N5X
60obj-y	+= clock_manager_n5x.o
61obj-y	+= lowlevel_init_soc64.o
62obj-y	+= mailbox_s10.o
63obj-y	+= misc_soc64.o
64obj-y	+= mmu-arm64_s10.o
65obj-y	+= reset_manager_s10.o
66obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= secure_vab.o
67obj-y	+= system_manager_soc64.o
68obj-y	+= timer_s10.o
69obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= vab.o
70obj-y	+= wrap_handoff_soc64.o
71obj-y	+= wrap_pll_config_soc64.o
72endif
73
74ifdef CONFIG_SPL_BUILD
75ifdef CONFIG_TARGET_SOCFPGA_GEN5
76obj-y	+= spl_gen5.o
77obj-y	+= freeze_controller.o
78obj-y	+= wrap_iocsr_config.o
79obj-y	+= wrap_pinmux_config.o
80obj-y	+= wrap_sdram_config.o
81endif
82ifdef CONFIG_TARGET_SOCFPGA_SOC64
83obj-y	+= firewall.o
84obj-y	+= spl_soc64.o
85endif
86ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
87obj-y	+= spl_a10.o
88endif
89ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
90obj-y	+= spl_s10.o
91endif
92ifdef CONFIG_TARGET_SOCFPGA_AGILEX
93obj-y	+= spl_agilex.o
94endif
95ifdef CONFIG_TARGET_SOCFPGA_N5X
96obj-y	+= spl_n5x.o
97endif
98else
99obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
100obj-$(CONFIG_SPL_ATF) += smc_api.o
101endif
102
103ifdef CONFIG_TARGET_SOCFPGA_GEN5
104# QTS-generated config file wrappers
105CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
106CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
107CFLAGS_wrap_pll_config.o	+= -I$(srctree)/board/$(BOARDDIR)
108CFLAGS_wrap_sdram_config.o	+= -I$(srctree)/board/$(BOARDDIR)
109endif
110