1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <common.h>
8 #include <asm/arch/clock_manager.h>
9 #include <asm/arch/firewall.h>
10 #include <asm/arch/mailbox_s10.h>
11 #include <asm/arch/misc.h>
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/u-boot.h>
17 #include <asm/utils.h>
18 #include <dm/uclass.h>
19 #include <hang.h>
20 #include <image.h>
21 #include <init.h>
22 #include <spl.h>
23 #include <watchdog.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
board_init_f(ulong dummy)27 void board_init_f(ulong dummy)
28 {
29 int ret;
30 struct udevice *dev;
31
32 ret = spl_early_init();
33 if (ret)
34 hang();
35
36 socfpga_get_managers_addr();
37
38 /* Ensure watchdog is paused when debugging is happening */
39 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
40 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
41
42 #ifdef CONFIG_HW_WATCHDOG
43 /* Enable watchdog before initializing the HW */
44 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
45 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
46 hw_watchdog_init();
47 #endif
48
49 /* ensure all processors are not released prior Linux boot */
50 writeq(0, CPU_RELEASE_ADDR);
51
52 timer_init();
53
54 sysmgr_pinmux_init();
55
56 preloader_console_init();
57
58 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
59 if (ret) {
60 printf("Clock init failed: %d\n", ret);
61 hang();
62 }
63
64 ret = uclass_get_device(UCLASS_CLK, 1, &dev);
65 if (ret) {
66 printf("Memory clock init failed: %d\n", ret);
67 hang();
68 }
69
70 print_reset_info();
71 cm_print_clock_quick_summary();
72
73 firewall_setup();
74
75 ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
76 if (ret) {
77 printf("CCU init failed: %d\n", ret);
78 hang();
79 }
80
81 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
82 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
83 if (ret) {
84 printf("DRAM init failed: %d\n", ret);
85 hang();
86 }
87 #endif
88
89 mbox_init();
90
91 #ifdef CONFIG_CADENCE_QSPI
92 mbox_qspi_open();
93 #endif
94 }
95