1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY LOGC_ARCH
7
8 #include <common.h>
9 #include <clk.h>
10 #include <cpu_func.h>
11 #include <debug_uart.h>
12 #include <env.h>
13 #include <init.h>
14 #include <log.h>
15 #include <lmb.h>
16 #include <misc.h>
17 #include <net.h>
18 #include <asm/io.h>
19 #include <asm/arch/stm32.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/global_data.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
24 #include <linux/bitops.h>
25 #include <spl.h>
26
27 /*
28 * early TLB into the .data section so that it not get cleared
29 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
30 */
31 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
32
33 struct lmb lmb;
34
get_bootmode(void)35 u32 get_bootmode(void)
36 {
37 /* read bootmode from TAMP backup register */
38 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
39 TAMP_BOOT_MODE_SHIFT;
40 }
41
42 /*
43 * weak function overidde: set the DDR/SYSRAM executable before to enable the
44 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
45 */
dram_bank_mmu_setup(int bank)46 void dram_bank_mmu_setup(int bank)
47 {
48 struct bd_info *bd = gd->bd;
49 int i;
50 phys_addr_t start;
51 phys_size_t size;
52 bool use_lmb = false;
53 enum dcache_option option;
54
55 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
56 /* STM32_SYSRAM_BASE exist only when SPL is supported */
57 #ifdef CONFIG_SPL
58 start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
59 size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
60 #endif
61 } else if (gd->flags & GD_FLG_RELOC) {
62 /* bd->bi_dram is available only after relocation */
63 start = bd->bi_dram[bank].start;
64 size = bd->bi_dram[bank].size;
65 use_lmb = true;
66 } else {
67 /* mark cacheable and executable the beggining of the DDR */
68 start = STM32_DDR_BASE;
69 size = CONFIG_DDR_CACHEABLE_SIZE;
70 }
71
72 for (i = start >> MMU_SECTION_SHIFT;
73 i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
74 i++) {
75 option = DCACHE_DEFAULT_OPTION;
76 if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
77 option = 0; /* INVALID ENTRY in TLB */
78 set_section_dcache(i, option);
79 }
80 }
81 /*
82 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
83 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
84 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
85 */
early_enable_caches(void)86 static void early_enable_caches(void)
87 {
88 /* I-cache is already enabled in start.S: cpu_init_cp15 */
89
90 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
91 return;
92
93 if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
94 gd->arch.tlb_size = PGTABLE_SIZE;
95 gd->arch.tlb_addr = (unsigned long)&early_tlb;
96 }
97
98 /* enable MMU (default configuration) */
99 dcache_enable();
100 }
101
102 /*
103 * Early system init
104 */
arch_cpu_init(void)105 int arch_cpu_init(void)
106 {
107 early_enable_caches();
108
109 /* early armv7 timer init: needed for polling */
110 timer_init();
111
112 return 0;
113 }
114
115 /* weak function for SOC specific initialization */
stm32mp_cpu_init(void)116 __weak void stm32mp_cpu_init(void)
117 {
118 }
119
mach_cpu_init(void)120 int mach_cpu_init(void)
121 {
122 u32 boot_mode;
123
124 stm32mp_cpu_init();
125
126 boot_mode = get_bootmode();
127
128 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
129 (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
130 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
131 else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
132 debug_uart_init();
133
134 return 0;
135 }
136
enable_caches(void)137 void enable_caches(void)
138 {
139 /* parse device tree when data cache is still activated */
140 lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
141
142 /* I-cache is already enabled in start.S: icache_enable() not needed */
143
144 /* deactivate the data cache, early enabled in arch_cpu_init() */
145 dcache_disable();
146 /*
147 * update MMU after relocation and enable the data cache
148 * warning: the TLB location udpated in board_f.c::reserve_mmu
149 */
150 dcache_enable();
151 }
152
153 /* used when CONFIG_DISPLAY_CPUINFO is activated */
print_cpuinfo(void)154 int print_cpuinfo(void)
155 {
156 char name[SOC_NAME_SIZE];
157
158 get_soc_name(name);
159 printf("CPU: %s\n", name);
160
161 return 0;
162 }
163
setup_boot_mode(void)164 static void setup_boot_mode(void)
165 {
166 const u32 serial_addr[] = {
167 STM32_USART1_BASE,
168 STM32_USART2_BASE,
169 STM32_USART3_BASE,
170 STM32_UART4_BASE,
171 STM32_UART5_BASE,
172 STM32_USART6_BASE,
173 STM32_UART7_BASE,
174 STM32_UART8_BASE
175 };
176 const u32 sdmmc_addr[] = {
177 STM32_SDMMC1_BASE,
178 STM32_SDMMC2_BASE,
179 STM32_SDMMC3_BASE
180 };
181 char cmd[60];
182 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
183 u32 boot_mode =
184 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
185 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
186 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
187 struct udevice *dev;
188
189 log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
190 __func__, boot_ctx, boot_mode, instance, forced_mode);
191 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
192 case BOOT_SERIAL_UART:
193 if (instance >= ARRAY_SIZE(serial_addr))
194 break;
195 /* serial : search associated node in devicetree */
196 sprintf(cmd, "serial@%x", serial_addr[instance]);
197 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
198 /* restore console on error */
199 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
200 gd->flags &= ~(GD_FLG_SILENT |
201 GD_FLG_DISABLE_CONSOLE);
202 log_err("uart%d = %s not found in device tree!\n",
203 instance + 1, cmd);
204 break;
205 }
206 sprintf(cmd, "%d", dev_seq(dev));
207 env_set("boot_device", "serial");
208 env_set("boot_instance", cmd);
209
210 /* restore console on uart when not used */
211 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
212 gd->flags &= ~(GD_FLG_SILENT |
213 GD_FLG_DISABLE_CONSOLE);
214 log_info("serial boot with console enabled!\n");
215 }
216 break;
217 case BOOT_SERIAL_USB:
218 env_set("boot_device", "usb");
219 env_set("boot_instance", "0");
220 break;
221 case BOOT_FLASH_SD:
222 case BOOT_FLASH_EMMC:
223 if (instance >= ARRAY_SIZE(sdmmc_addr))
224 break;
225 /* search associated sdmmc node in devicetree */
226 sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
227 if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
228 printf("mmc%d = %s not found in device tree!\n",
229 instance, cmd);
230 break;
231 }
232 sprintf(cmd, "%d", dev_seq(dev));
233 env_set("boot_device", "mmc");
234 env_set("boot_instance", cmd);
235 break;
236 case BOOT_FLASH_NAND:
237 env_set("boot_device", "nand");
238 env_set("boot_instance", "0");
239 break;
240 case BOOT_FLASH_SPINAND:
241 env_set("boot_device", "spi-nand");
242 env_set("boot_instance", "0");
243 break;
244 case BOOT_FLASH_NOR:
245 env_set("boot_device", "nor");
246 env_set("boot_instance", "0");
247 break;
248 default:
249 env_set("boot_device", "invalid");
250 env_set("boot_instance", "");
251 log_err("unexpected boot mode = %x\n", boot_mode);
252 break;
253 }
254
255 switch (forced_mode) {
256 case BOOT_FASTBOOT:
257 log_info("Enter fastboot!\n");
258 env_set("preboot", "env set preboot; fastboot 0");
259 break;
260 case BOOT_STM32PROG:
261 env_set("boot_device", "usb");
262 env_set("boot_instance", "0");
263 break;
264 case BOOT_UMS_MMC0:
265 case BOOT_UMS_MMC1:
266 case BOOT_UMS_MMC2:
267 log_info("Enter UMS!\n");
268 instance = forced_mode - BOOT_UMS_MMC0;
269 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
270 env_set("preboot", cmd);
271 break;
272 case BOOT_RECOVERY:
273 env_set("preboot", "env set preboot; run altbootcmd");
274 break;
275 case BOOT_NORMAL:
276 break;
277 default:
278 log_debug("unexpected forced boot mode = %x\n", forced_mode);
279 break;
280 }
281
282 /* clear TAMP for next reboot */
283 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
284 }
285
286 /*
287 * If there is no MAC address in the environment, then it will be initialized
288 * (silently) from the value in the OTP.
289 */
setup_mac_address(void)290 __weak int setup_mac_address(void)
291 {
292 int ret;
293 int i;
294 u32 otp[3];
295 uchar enetaddr[6];
296 struct udevice *dev;
297 int nb_eth, nb_otp, index;
298
299 if (!IS_ENABLED(CONFIG_NET))
300 return 0;
301
302 nb_eth = get_eth_nb();
303
304 /* 6 bytes for each MAC addr and 4 bytes for each OTP */
305 nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);
306
307 ret = uclass_get_device_by_driver(UCLASS_MISC,
308 DM_DRIVER_GET(stm32mp_bsec),
309 &dev);
310 if (ret)
311 return ret;
312
313 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
314 if (ret < 0)
315 return ret;
316
317 for (index = 0; index < nb_eth; index++) {
318 /* MAC already in environment */
319 if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
320 continue;
321
322 for (i = 0; i < 6; i++)
323 enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index];
324
325 if (!is_valid_ethaddr(enetaddr)) {
326 log_err("invalid MAC address %d in OTP %pM\n",
327 index, enetaddr);
328 return -EINVAL;
329 }
330 log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
331 ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
332 if (ret) {
333 log_err("Failed to set mac address %pM from OTP: %d\n",
334 enetaddr, ret);
335 return ret;
336 }
337 }
338
339 return 0;
340 }
341
setup_serial_number(void)342 static int setup_serial_number(void)
343 {
344 char serial_string[25];
345 u32 otp[3] = {0, 0, 0 };
346 struct udevice *dev;
347 int ret;
348
349 if (env_get("serial#"))
350 return 0;
351
352 ret = uclass_get_device_by_driver(UCLASS_MISC,
353 DM_DRIVER_GET(stm32mp_bsec),
354 &dev);
355 if (ret)
356 return ret;
357
358 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
359 otp, sizeof(otp));
360 if (ret < 0)
361 return ret;
362
363 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
364 env_set("serial#", serial_string);
365
366 return 0;
367 }
368
stm32mp_misc_init(void)369 __weak void stm32mp_misc_init(void)
370 {
371 }
372
arch_misc_init(void)373 int arch_misc_init(void)
374 {
375 setup_boot_mode();
376 setup_mac_address();
377 setup_serial_number();
378 stm32mp_misc_init();
379
380 return 0;
381 }
382
383 /*
384 * Without forcing the ".data" section, this would get saved in ".bss". BSS
385 * will be cleared soon after, so it's not suitable.
386 */
387 static uintptr_t rom_api_table __section(".data");
388 static uintptr_t nt_fw_dtb __section(".data");
389
390 /*
391 * The ROM gives us the API location in r0 when starting. This is only available
392 * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
393 * the FDT address provided by TF-A in r2 at boot time. This function is called
394 * from start.S
395 */
save_boot_params(unsigned long r0,unsigned long r1,unsigned long r2,unsigned long r3)396 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
397 unsigned long r3)
398 {
399 if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
400 rom_api_table = r0;
401
402 if (IS_ENABLED(CONFIG_TFABOOT))
403 nt_fw_dtb = r2;
404
405 save_boot_params_ret();
406 }
407
get_stm32mp_rom_api_table(void)408 uintptr_t get_stm32mp_rom_api_table(void)
409 {
410 return rom_api_table;
411 }
412
get_stm32mp_bl2_dtb(void)413 uintptr_t get_stm32mp_bl2_dtb(void)
414 {
415 return nt_fw_dtb;
416 }
417
418 #ifdef CONFIG_SPL_BUILD
jump_to_image_no_args(struct spl_image_info * spl_image)419 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
420 {
421 typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
422 uintptr_t romapi = get_stm32mp_rom_api_table();
423
424 image_entry_stm32_t image_entry =
425 (image_entry_stm32_t)spl_image->entry_point;
426
427 printf("image entry point: 0x%lx\n", spl_image->entry_point);
428 image_entry(romapi);
429 }
430 #endif
431