1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _MACH_STM32_H_ 7 #define _MACH_STM32_H_ 8 9 #ifndef __ASSEMBLY__ 10 #include <linux/bitops.h> 11 #endif 12 13 /* 14 * Peripheral memory map 15 * only address used before device tree parsing 16 */ 17 #define STM32_RCC_BASE 0x50000000 18 #define STM32_PWR_BASE 0x50001000 19 #define STM32_SYSCFG_BASE 0x50020000 20 #ifdef CONFIG_STM32MP15x 21 #define STM32_DBGMCU_BASE 0x50081000 22 #endif 23 #define STM32_FMC2_BASE 0x58002000 24 #define STM32_DDRCTRL_BASE 0x5A003000 25 #define STM32_DDRPHYC_BASE 0x5A004000 26 #define STM32_TZC_BASE 0x5C006000 27 #define STM32_ETZPC_BASE 0x5C007000 28 #define STM32_STGEN_BASE 0x5C008000 29 #define STM32_TAMP_BASE 0x5C00A000 30 31 #ifdef CONFIG_STM32MP15x 32 #define STM32_USART1_BASE 0x5C000000 33 #define STM32_USART2_BASE 0x4000E000 34 #endif 35 #ifdef CONFIG_STM32MP13x 36 #define STM32_USART1_BASE 0x4c000000 37 #define STM32_USART2_BASE 0x4c001000 38 #endif 39 #define STM32_USART3_BASE 0x4000F000 40 #define STM32_UART4_BASE 0x40010000 41 #define STM32_UART5_BASE 0x40011000 42 #define STM32_USART6_BASE 0x44003000 43 #define STM32_UART7_BASE 0x40018000 44 #define STM32_UART8_BASE 0x40019000 45 46 #define STM32_SDMMC1_BASE 0x58005000 47 #define STM32_SDMMC2_BASE 0x58007000 48 #define STM32_SDMMC3_BASE 0x48004000 49 50 #ifdef CONFIG_STM32MP15x 51 #define STM32_SYSRAM_BASE 0x2FFC0000 52 #define STM32_SYSRAM_SIZE SZ_256K 53 #endif 54 55 #define STM32_DDR_BASE 0xC0000000 56 #define STM32_DDR_SIZE SZ_1G 57 58 #ifndef __ASSEMBLY__ 59 /* enumerated used to identify the SYSCON driver instance */ 60 enum { 61 STM32MP_SYSCON_UNKNOWN, 62 STM32MP_SYSCON_SYSCFG, 63 }; 64 65 /* 66 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT 67 * - boot device = bit 8:4 68 * - boot instance = bit 3:0 69 */ 70 #define BOOT_TYPE_MASK 0xF0 71 #define BOOT_TYPE_SHIFT 4 72 #define BOOT_INSTANCE_MASK 0x0F 73 #define BOOT_INSTANCE_SHIFT 0 74 75 enum boot_device { 76 BOOT_FLASH_SD = 0x10, 77 BOOT_FLASH_SD_1 = 0x11, 78 BOOT_FLASH_SD_2 = 0x12, 79 BOOT_FLASH_SD_3 = 0x13, 80 81 BOOT_FLASH_EMMC = 0x20, 82 BOOT_FLASH_EMMC_1 = 0x21, 83 BOOT_FLASH_EMMC_2 = 0x22, 84 BOOT_FLASH_EMMC_3 = 0x23, 85 86 BOOT_FLASH_NAND = 0x30, 87 BOOT_FLASH_NAND_FMC = 0x31, 88 89 BOOT_FLASH_NOR = 0x40, 90 BOOT_FLASH_NOR_QSPI = 0x41, 91 92 BOOT_SERIAL_UART = 0x50, 93 BOOT_SERIAL_UART_1 = 0x51, 94 BOOT_SERIAL_UART_2 = 0x52, 95 BOOT_SERIAL_UART_3 = 0x53, 96 BOOT_SERIAL_UART_4 = 0x54, 97 BOOT_SERIAL_UART_5 = 0x55, 98 BOOT_SERIAL_UART_6 = 0x56, 99 BOOT_SERIAL_UART_7 = 0x57, 100 BOOT_SERIAL_UART_8 = 0x58, 101 102 BOOT_SERIAL_USB = 0x60, 103 BOOT_SERIAL_USB_OTG = 0x62, 104 105 BOOT_FLASH_SPINAND = 0x70, 106 BOOT_FLASH_SPINAND_1 = 0x71, 107 }; 108 109 /* TAMP registers */ 110 #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) 111 112 #ifdef CONFIG_STM32MP15x 113 #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) 114 #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) 115 #define TAMP_FWU_BOOT_INFO_REG TAMP_BACKUP_REGISTER(10) 116 #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) 117 #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) 118 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) 119 #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) 120 121 #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) 122 123 #define TAMP_FWU_BOOT_IDX_OFFSET 0 124 125 #define TAMP_COPRO_STATE_OFF 0 126 #define TAMP_COPRO_STATE_INIT 1 127 #define TAMP_COPRO_STATE_CRUN 2 128 #define TAMP_COPRO_STATE_CSTOP 3 129 #define TAMP_COPRO_STATE_STANDBY 4 130 #define TAMP_COPRO_STATE_CRASH 5 131 #endif 132 133 #ifdef CONFIG_STM32MP13x 134 #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) 135 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) 136 #endif 137 138 #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) 139 #define TAMP_BOOT_MODE_SHIFT 8 140 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) 141 #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) 142 #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) 143 144 enum forced_boot_mode { 145 BOOT_NORMAL = 0x00, 146 BOOT_FASTBOOT = 0x01, 147 BOOT_RECOVERY = 0x02, 148 BOOT_STM32PROG = 0x03, 149 BOOT_UMS_MMC0 = 0x10, 150 BOOT_UMS_MMC1 = 0x11, 151 BOOT_UMS_MMC2 = 0x12, 152 }; 153 154 /* offset used for BSEC driver: misc_read and misc_write */ 155 #define STM32_BSEC_SHADOW_OFFSET 0x0 156 #define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4) 157 #define STM32_BSEC_OTP_OFFSET 0x80000000 158 #define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4) 159 #define STM32_BSEC_LOCK_OFFSET 0xC0000000 160 #define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) 161 162 /* BSEC OTP index */ 163 #ifdef CONFIG_STM32MP15x 164 #define BSEC_OTP_RPN 1 165 #define BSEC_OTP_SERIAL 13 166 #define BSEC_OTP_PKG 16 167 #define BSEC_OTP_MAC 57 168 #define BSEC_OTP_BOARD 59 169 #endif 170 #ifdef CONFIG_STM32MP13x 171 #define BSEC_OTP_RPN 1 172 #define BSEC_OTP_SERIAL 13 173 #define BSEC_OTP_MAC 57 174 #define BSEC_OTP_BOARD 60 175 #endif 176 177 #endif /* __ASSEMBLY__ */ 178 #endif /* _MACH_STM32_H_ */ 179