1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 /* Tegra114 Clock control functions */
8
9 #include <common.h>
10 #include <init.h>
11 #include <log.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sysctr.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
18 #include <div64.h>
19 #include <fdtdec.h>
20 #include <linux/delay.h>
21
22 #include <dt-bindings/clock/tegra114-car.h>
23
24 /*
25 * Clock types that we can use as a source. The Tegra114 has muxes for the
26 * peripheral clocks, and in most cases there are four options for the clock
27 * source. This gives us a clock 'type' and exploits what commonality exists
28 * in the device.
29 *
30 * Letters are obvious, except for T which means CLK_M, and S which means the
31 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
32 * datasheet) and PLL_M are different things. The former is the basic
33 * clock supplied to the SOC from an external oscillator. The latter is the
34 * memory clock PLL.
35 *
36 * See definitions in clock_id in the header file.
37 */
38 enum clock_type_id {
39 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
40 CLOCK_TYPE_MCPA, /* and so on */
41 CLOCK_TYPE_MCPT,
42 CLOCK_TYPE_PCM,
43 CLOCK_TYPE_PCMT,
44 CLOCK_TYPE_PCMT16,
45 CLOCK_TYPE_PDCT,
46 CLOCK_TYPE_ACPT,
47 CLOCK_TYPE_ASPTE,
48 CLOCK_TYPE_PMDACD2T,
49 CLOCK_TYPE_PCST,
50
51 CLOCK_TYPE_COUNT,
52 CLOCK_TYPE_NONE = -1, /* invalid clock type */
53 };
54
55 enum {
56 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
57 };
58
59 /*
60 * Clock source mux for each clock type. This just converts our enum into
61 * a list of mux sources for use by the code.
62 *
63 * Note:
64 * The extra column in each clock source array is used to store the mask
65 * bits in its register for the source.
66 */
67 #define CLK(x) CLOCK_ID_ ## x
68 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
69 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
70 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
71 MASK_BITS_31_30},
72 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
73 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
74 MASK_BITS_31_30},
75 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
76 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
77 MASK_BITS_31_30},
78 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
79 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
80 MASK_BITS_31_30},
81 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
82 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
83 MASK_BITS_31_30},
84 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
85 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
86 MASK_BITS_31_30},
87 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
88 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
89 MASK_BITS_31_30},
90 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
91 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
92 MASK_BITS_31_30},
93 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
94 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
95 MASK_BITS_31_29},
96 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
97 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
98 MASK_BITS_31_29},
99 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
100 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
101 MASK_BITS_31_28}
102 };
103
104 /*
105 * Clock type for each peripheral clock source. We put the name in each
106 * record just so it is easy to match things up
107 */
108 #define TYPE(name, type) type
109 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
110 /* 0x00 */
111 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
112 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
113 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
114 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
115 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
116 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
117 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
118 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
119
120 /* 0x08 */
121 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
122 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
123 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
124 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
125 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
126 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
127 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
128 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
129
130 /* 0x10 */
131 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
132 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
133 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
134 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
135 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
136 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
137 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
138 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
139
140 /* 0x18 */
141 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
142 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
143 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
144 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
145 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
146 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
147 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
148 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
149
150 /* 0x20 */
151 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
152 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
153 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
154 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
155 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
156 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
157 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
158 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
159
160 /* 0x28 */
161 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
162 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
163 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
164 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
165 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
166 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
167 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
168 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
169
170 /* 0x30 */
171 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
173 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
174 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
175 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
176 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
178 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
179
180 /* 0x38h */ /* Jumps to reg offset 0x3B0h */
181 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
182 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
183 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
184 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
185 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
186 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
187 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
189
190 /* 0x40 */
191 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
192 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
193 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
194 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
195 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
196 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
197 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
198 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
199
200 /* 0x48 */
201 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
202 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
203 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
204 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
205 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
209
210 /* 0x50 */
211 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
214 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
215 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
216 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
217 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
218 };
219
220 /*
221 * This array translates a periph_id to a periphc_internal_id
222 *
223 * Not present/matched up:
224 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
225 * SPDIF - which is both 0x08 and 0x0c
226 *
227 */
228 #define NONE(name) (-1)
229 #define OFFSET(name, value) PERIPHC_ ## name
230 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
231 /* Low word: 31:0 */
232 NONE(CPU),
233 NONE(COP),
234 NONE(TRIGSYS),
235 NONE(RESERVED3),
236 NONE(RTC),
237 NONE(TMR),
238 PERIPHC_UART1,
239 PERIPHC_UART2, /* and vfir 0x68 */
240
241 /* 8 */
242 NONE(GPIO),
243 PERIPHC_SDMMC2,
244 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
245 PERIPHC_I2S1,
246 PERIPHC_I2C1,
247 PERIPHC_NDFLASH,
248 PERIPHC_SDMMC1,
249 PERIPHC_SDMMC4,
250
251 /* 16 */
252 NONE(RESERVED16),
253 PERIPHC_PWM,
254 PERIPHC_I2S2,
255 PERIPHC_EPP,
256 PERIPHC_VI,
257 PERIPHC_G2D,
258 NONE(USBD),
259 NONE(ISP),
260
261 /* 24 */
262 PERIPHC_G3D,
263 NONE(RESERVED25),
264 PERIPHC_DISP2,
265 PERIPHC_DISP1,
266 PERIPHC_HOST1X,
267 NONE(VCP),
268 PERIPHC_I2S0,
269 NONE(CACHE2),
270
271 /* Middle word: 63:32 */
272 NONE(MEM),
273 NONE(AHBDMA),
274 NONE(APBDMA),
275 NONE(RESERVED35),
276 NONE(RESERVED36),
277 NONE(STAT_MON),
278 NONE(RESERVED38),
279 NONE(RESERVED39),
280
281 /* 40 */
282 NONE(KFUSE),
283 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
284 PERIPHC_NOR,
285 NONE(RESERVED43),
286 PERIPHC_SBC2,
287 NONE(RESERVED45),
288 PERIPHC_SBC3,
289 PERIPHC_I2C5,
290
291 /* 48 */
292 NONE(DSI),
293 PERIPHC_TVO, /* also CVE 0x40 */
294 PERIPHC_MIPI,
295 PERIPHC_HDMI,
296 NONE(CSI),
297 PERIPHC_TVDAC,
298 PERIPHC_I2C2,
299 PERIPHC_UART3,
300
301 /* 56 */
302 NONE(RESERVED56),
303 PERIPHC_EMC,
304 NONE(USB2),
305 NONE(USB3),
306 PERIPHC_MPE,
307 PERIPHC_VDE,
308 NONE(BSEA),
309 NONE(BSEV),
310
311 /* Upper word 95:64 */
312 PERIPHC_SPEEDO,
313 PERIPHC_UART4,
314 PERIPHC_UART5,
315 PERIPHC_I2C3,
316 PERIPHC_SBC4,
317 PERIPHC_SDMMC3,
318 NONE(PCIE),
319 PERIPHC_OWR,
320
321 /* 72 */
322 NONE(AFI),
323 PERIPHC_CSITE,
324 NONE(PCIEXCLK),
325 NONE(AVPUCQ),
326 NONE(RESERVED76),
327 NONE(RESERVED77),
328 NONE(RESERVED78),
329 NONE(DTV),
330
331 /* 80 */
332 PERIPHC_NANDSPEED,
333 PERIPHC_I2CSLOW,
334 NONE(DSIB),
335 NONE(RESERVED83),
336 NONE(IRAMA),
337 NONE(IRAMB),
338 NONE(IRAMC),
339 NONE(IRAMD),
340
341 /* 88 */
342 NONE(CRAM2),
343 NONE(RESERVED89),
344 NONE(MDOUBLER),
345 NONE(RESERVED91),
346 NONE(SUSOUT),
347 NONE(RESERVED93),
348 NONE(RESERVED94),
349 NONE(RESERVED95),
350
351 /* V word: 31:0 */
352 NONE(CPUG),
353 NONE(CPULP),
354 PERIPHC_G3D2,
355 PERIPHC_MSELECT,
356 PERIPHC_TSENSOR,
357 PERIPHC_I2S3,
358 PERIPHC_I2S4,
359 PERIPHC_I2C4,
360
361 /* 08 */
362 PERIPHC_SBC5,
363 PERIPHC_SBC6,
364 PERIPHC_AUDIO,
365 NONE(APBIF),
366 PERIPHC_DAM0,
367 PERIPHC_DAM1,
368 PERIPHC_DAM2,
369 PERIPHC_HDA2CODEC2X,
370
371 /* 16 */
372 NONE(ATOMICS),
373 NONE(RESERVED17),
374 NONE(RESERVED18),
375 NONE(RESERVED19),
376 NONE(RESERVED20),
377 NONE(RESERVED21),
378 NONE(RESERVED22),
379 PERIPHC_ACTMON,
380
381 /* 24 */
382 NONE(RESERVED24),
383 NONE(RESERVED25),
384 NONE(RESERVED26),
385 NONE(RESERVED27),
386 PERIPHC_SATA,
387 PERIPHC_HDA,
388 NONE(RESERVED30),
389 NONE(RESERVED31),
390
391 /* W word: 31:0 */
392 NONE(HDA2HDMICODEC),
393 NONE(RESERVED1_SATACOLD),
394 NONE(RESERVED2_PCIERX0),
395 NONE(RESERVED3_PCIERX1),
396 NONE(RESERVED4_PCIERX2),
397 NONE(RESERVED5_PCIERX3),
398 NONE(RESERVED6_PCIERX4),
399 NONE(RESERVED7_PCIERX5),
400
401 /* 40 */
402 NONE(CEC),
403 NONE(PCIE2_IOBIST),
404 NONE(EMC_IOBIST),
405 NONE(HDMI_IOBIST),
406 NONE(SATA_IOBIST),
407 NONE(MIPI_IOBIST),
408 NONE(EMC1_IOBIST),
409 NONE(XUSB),
410
411 /* 48 */
412 NONE(CILAB),
413 NONE(CILCD),
414 NONE(CILE),
415 NONE(DSIA_LP),
416 NONE(DSIB_LP),
417 NONE(RESERVED21_ENTROPY),
418 NONE(RESERVED22_W),
419 NONE(RESERVED23_W),
420
421 /* 56 */
422 NONE(RESERVED24_W),
423 NONE(AMX0),
424 NONE(ADX0),
425 NONE(DVFS),
426 NONE(XUSB_SS),
427 NONE(EMC_DLL),
428 NONE(MC1),
429 NONE(EMC1),
430 };
431
432 /*
433 * PLL divider shift/mask tables for all PLL IDs.
434 */
435 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
436 /*
437 * T114: some deviations from T2x/T30.
438 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
439 * If lock_ena or lock_det are >31, they're not used in that PLL.
440 */
441
442 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
443 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
444 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
445 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
446 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
447 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
448 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
449 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
450 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
451 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
452 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
453 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
454 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
455 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
456 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
457 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
458 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
459 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
460 };
461
462 /*
463 * Get the oscillator frequency, from the corresponding hardware configuration
464 * field. Note that T30+ supports 3 new higher freqs.
465 */
clock_get_osc_freq(void)466 enum clock_osc_freq clock_get_osc_freq(void)
467 {
468 struct clk_rst_ctlr *clkrst =
469 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
470 u32 reg;
471
472 reg = readl(&clkrst->crc_osc_ctrl);
473 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
474 }
475
476 /* Returns a pointer to the clock source register for a peripheral */
get_periph_source_reg(enum periph_id periph_id)477 u32 *get_periph_source_reg(enum periph_id periph_id)
478 {
479 struct clk_rst_ctlr *clkrst =
480 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
481 enum periphc_internal_id internal_id;
482
483 /* Coresight is a special case */
484 if (periph_id == PERIPH_ID_CSI)
485 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
486
487 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
488 internal_id = periph_id_to_internal_id[periph_id];
489 assert(internal_id != -1);
490 if (internal_id >= PERIPHC_VW_FIRST) {
491 internal_id -= PERIPHC_VW_FIRST;
492 return &clkrst->crc_clk_src_vw[internal_id];
493 } else
494 return &clkrst->crc_clk_src[internal_id];
495 }
496
get_periph_clock_info(enum periph_id periph_id,int * mux_bits,int * divider_bits,int * type)497 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
498 int *divider_bits, int *type)
499 {
500 enum periphc_internal_id internal_id;
501
502 if (!clock_periph_id_isvalid(periph_id))
503 return -1;
504
505 internal_id = periph_id_to_internal_id[periph_id];
506 if (!periphc_internal_id_isvalid(internal_id))
507 return -1;
508
509 *type = clock_periph_type[internal_id];
510 if (!clock_type_id_isvalid(*type))
511 return -1;
512
513 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
514
515 if (*type == CLOCK_TYPE_PCMT16)
516 *divider_bits = 16;
517 else
518 *divider_bits = 8;
519
520 return 0;
521 }
522
get_periph_clock_id(enum periph_id periph_id,int source)523 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
524 {
525 enum periphc_internal_id internal_id;
526 int type;
527
528 if (!clock_periph_id_isvalid(periph_id))
529 return CLOCK_ID_NONE;
530
531 internal_id = periph_id_to_internal_id[periph_id];
532 if (!periphc_internal_id_isvalid(internal_id))
533 return CLOCK_ID_NONE;
534
535 type = clock_periph_type[internal_id];
536 if (!clock_type_id_isvalid(type))
537 return CLOCK_ID_NONE;
538
539 return clock_source[type][source];
540 }
541
542 /**
543 * Given a peripheral ID and the required source clock, this returns which
544 * value should be programmed into the source mux for that peripheral.
545 *
546 * There is special code here to handle the one source type with 5 sources.
547 *
548 * @param periph_id peripheral to start
549 * @param source PLL id of required parent clock
550 * @param mux_bits Set to number of bits in mux register: 2 or 4
551 * @param divider_bits Set to number of divider bits (8 or 16)
552 * Return: mux value (0-4, or -1 if not found)
553 */
get_periph_clock_source(enum periph_id periph_id,enum clock_id parent,int * mux_bits,int * divider_bits)554 int get_periph_clock_source(enum periph_id periph_id,
555 enum clock_id parent, int *mux_bits, int *divider_bits)
556 {
557 enum clock_type_id type;
558 int mux, err;
559
560 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
561 assert(!err);
562
563 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
564 if (clock_source[type][mux] == parent)
565 return mux;
566
567 /* if we get here, either us or the caller has made a mistake */
568 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
569 parent);
570 return -1;
571 }
572
clock_set_enable(enum periph_id periph_id,int enable)573 void clock_set_enable(enum periph_id periph_id, int enable)
574 {
575 struct clk_rst_ctlr *clkrst =
576 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
577 u32 *clk;
578 u32 reg;
579
580 /* Enable/disable the clock to this peripheral */
581 assert(clock_periph_id_isvalid(periph_id));
582 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
583 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
584 else
585 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
586 reg = readl(clk);
587 if (enable)
588 reg |= PERIPH_MASK(periph_id);
589 else
590 reg &= ~PERIPH_MASK(periph_id);
591 writel(reg, clk);
592 }
593
reset_set_enable(enum periph_id periph_id,int enable)594 void reset_set_enable(enum periph_id periph_id, int enable)
595 {
596 struct clk_rst_ctlr *clkrst =
597 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
598 u32 *reset;
599 u32 reg;
600
601 /* Enable/disable reset to the peripheral */
602 assert(clock_periph_id_isvalid(periph_id));
603 if (periph_id < PERIPH_ID_VW_FIRST)
604 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
605 else
606 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
607 reg = readl(reset);
608 if (enable)
609 reg |= PERIPH_MASK(periph_id);
610 else
611 reg &= ~PERIPH_MASK(periph_id);
612 writel(reg, reset);
613 }
614
615 #if CONFIG_IS_ENABLED(OF_CONTROL)
616 /*
617 * Convert a device tree clock ID to our peripheral ID. They are mostly
618 * the same but we are very cautious so we check that a valid clock ID is
619 * provided.
620 *
621 * @param clk_id Clock ID according to tegra114 device tree binding
622 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
623 */
clk_id_to_periph_id(int clk_id)624 enum periph_id clk_id_to_periph_id(int clk_id)
625 {
626 if (clk_id > PERIPH_ID_COUNT)
627 return PERIPH_ID_NONE;
628
629 switch (clk_id) {
630 case PERIPH_ID_RESERVED3:
631 case PERIPH_ID_RESERVED16:
632 case PERIPH_ID_RESERVED24:
633 case PERIPH_ID_RESERVED35:
634 case PERIPH_ID_RESERVED43:
635 case PERIPH_ID_RESERVED45:
636 case PERIPH_ID_RESERVED56:
637 case PERIPH_ID_RESERVED76:
638 case PERIPH_ID_RESERVED77:
639 case PERIPH_ID_RESERVED78:
640 case PERIPH_ID_RESERVED83:
641 case PERIPH_ID_RESERVED89:
642 case PERIPH_ID_RESERVED91:
643 case PERIPH_ID_RESERVED93:
644 case PERIPH_ID_RESERVED94:
645 case PERIPH_ID_RESERVED95:
646 return PERIPH_ID_NONE;
647 default:
648 return clk_id;
649 }
650 }
651
652 /*
653 * Convert a device tree clock ID to our PLL ID.
654 *
655 * @param clk_id Clock ID according to tegra114 device tree binding
656 * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
657 */
clk_id_to_pll_id(int clk_id)658 enum clock_id clk_id_to_pll_id(int clk_id)
659 {
660 switch (clk_id) {
661 case TEGRA114_CLK_PLL_C:
662 return CLOCK_ID_CGENERAL;
663 case TEGRA114_CLK_PLL_M:
664 return CLOCK_ID_MEMORY;
665 case TEGRA114_CLK_PLL_P:
666 return CLOCK_ID_PERIPH;
667 case TEGRA114_CLK_PLL_A:
668 return CLOCK_ID_AUDIO;
669 case TEGRA114_CLK_PLL_U:
670 return CLOCK_ID_USB;
671 case TEGRA114_CLK_PLL_D:
672 case TEGRA114_CLK_PLL_D_OUT0:
673 return CLOCK_ID_DISPLAY;
674 case TEGRA114_CLK_PLL_X:
675 return CLOCK_ID_XCPU;
676 case TEGRA114_CLK_PLL_E_OUT0:
677 return CLOCK_ID_EPCI;
678 case TEGRA114_CLK_CLK_32K:
679 return CLOCK_ID_32KHZ;
680 case TEGRA114_CLK_CLK_M:
681 return CLOCK_ID_CLK_M;
682 default:
683 return CLOCK_ID_NONE;
684 }
685 }
686 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
687
clock_early_init(void)688 void clock_early_init(void)
689 {
690 struct clk_rst_ctlr *clkrst =
691 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
692 struct clk_pll_info *pllinfo;
693 u32 data;
694
695 tegra30_set_up_pllp();
696
697 /* clear IDDQ before accessing any other PLLC registers */
698 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
699 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
700 udelay(2);
701
702 /*
703 * PLLC output frequency set to 600Mhz
704 * PLLD output frequency set to 925Mhz
705 */
706 switch (clock_get_osc_freq()) {
707 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
708 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
709 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
710 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
711 break;
712
713 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
714 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
715 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
716 break;
717
718 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
719 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
720 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
721 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
722 break;
723 case CLOCK_OSC_FREQ_19_2:
724 case CLOCK_OSC_FREQ_38_4:
725 default:
726 /*
727 * These are not supported. It is too early to print a
728 * message and the UART likely won't work anyway due to the
729 * oscillator being wrong.
730 */
731 break;
732 }
733
734 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
735 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
736
737 /* PLLC_MISC: Set LOCK_ENABLE */
738 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
739 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
740 udelay(2);
741
742 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
743 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
744 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
745 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
746 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
747 udelay(2);
748 }
749
arch_timer_init(void)750 void arch_timer_init(void)
751 {
752 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
753 u32 freq, val;
754
755 freq = clock_get_rate(CLOCK_ID_CLK_M);
756 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
757
758 /* ARM CNTFRQ */
759 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
760
761 /* Only T114 has the System Counter regs */
762 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
763 writel(freq, &sysctr->cntfid0);
764
765 val = readl(&sysctr->cntcr);
766 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
767 writel(val, &sysctr->cntcr);
768 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
769 }
770
771 struct periph_clk_init periph_clk_init_table[] = {
772 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
773 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
774 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
775 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
776 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
777 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
778 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
779 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
780 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
781 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
782 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
783 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
784 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
785 { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
786 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
787 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
788 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
789 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
790 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
791 { -1, },
792 };
793