1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010 - 2011
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <linux/errno.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/emc.h>
13 #include <asm/arch/gp_padctrl.h>
14 #include <asm/arch/pinmux.h>
15 #include <asm/arch/sdram_param.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/apb_misc.h>
19 #include <asm/arch-tegra/clk_rst.h>
20 #include <asm/arch-tegra/pmc.h>
21 #include <asm/arch-tegra/fuse.h>
22 #include <asm/arch-tegra/warmboot.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 /*
27 * This is the place in SRAM where the SDRAM parameters are stored. There
28 * are 4 blocks, one for each RAM code
29 */
30 #define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
31
32 /* TODO: If we later add support for the Misc GP controller, refactor this */
33 union xm2cfga_reg {
34 struct {
35 u32 reserved0:2;
36 u32 hsm_en:1;
37 u32 reserved1:2;
38 u32 preemp_en:1;
39 u32 vref_en:1;
40 u32 reserved2:5;
41 u32 cal_drvdn:5;
42 u32 reserved3:3;
43 u32 cal_drvup:5;
44 u32 reserved4:3;
45 u32 cal_drvdn_slwr:2;
46 u32 cal_drvup_slwf:2;
47 };
48 u32 word;
49 };
50
51 union xm2cfgd_reg {
52 struct {
53 u32 reserved0:2;
54 u32 hsm_en:1;
55 u32 schmt_en:1;
56 u32 lpmd:2;
57 u32 vref_en:1;
58 u32 reserved1:5;
59 u32 cal_drvdn:5;
60 u32 reserved2:3;
61 u32 cal_drvup:5;
62 u32 reserved3:3;
63 u32 cal_drvdn_slwr:2;
64 u32 cal_drvup_slwf:2;
65 };
66 u32 word;
67 };
68
69 /*
70 * TODO: This register is not documented in the TRM yet. We could move this
71 * into the EMC and give it a proper interface, but not while it is
72 * undocumented.
73 */
74 union fbio_spare_reg {
75 struct {
76 u32 reserved:24;
77 u32 cfg_wb0:8;
78 };
79 u32 word;
80 };
81
82 /* We pack the resume information into these unions for later */
83 union scratch2_reg {
84 struct {
85 u32 pllm_base_divm:5;
86 u32 pllm_base_divn:10;
87 u32 pllm_base_divp:3;
88 u32 pllm_misc_lfcon:4;
89 u32 pllm_misc_cpcon:4;
90 u32 gp_xm2cfga_padctrl_preemp:1;
91 u32 gp_xm2cfgd_padctrl_schmt:1;
92 u32 osc_ctrl_xobp:1;
93 u32 memory_type:3;
94 };
95 u32 word;
96 };
97
98 union scratch4_reg {
99 struct {
100 u32 emc_clock_divider:8;
101 u32 pllm_stable_time:8;
102 u32 pllx_stable_time:8;
103 u32 emc_fbio_spare_cfg_wb0:8;
104 };
105 u32 word;
106 };
107
108 union scratch24_reg {
109 struct {
110 u32 emc_auto_cal_wait:8;
111 u32 emc_pin_program_wait:8;
112 u32 warmboot_wait:8;
113 u32 reserved:8;
114 };
115 u32 word;
116 };
117
warmboot_save_sdram_params(void)118 int warmboot_save_sdram_params(void)
119 {
120 u32 ram_code;
121 struct sdram_params sdram;
122 struct apb_misc_pp_ctlr *apb_misc =
123 (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
124 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
125 struct apb_misc_gp_ctlr *gp =
126 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
127 struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
128 union scratch2_reg scratch2;
129 union scratch4_reg scratch4;
130 union scratch24_reg scratch24;
131 union xm2cfga_reg xm2cfga;
132 union xm2cfgd_reg xm2cfgd;
133 union fbio_spare_reg fbio_spare;
134
135 /* get ram code that is used as index to array sdram_params in BCT */
136 ram_code = (readl(&apb_misc->strapping_opt_a) >>
137 STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
138 memcpy(&sdram,
139 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
140 sizeof(sdram));
141
142 xm2cfga.word = readl(&gp->xm2cfga);
143 xm2cfgd.word = readl(&gp->xm2cfgd);
144
145 scratch2.word = 0;
146 scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
147
148 /* Get the memory PLL settings */
149 {
150 u32 divm, divn, divp, cpcon, lfcon;
151
152 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
153 &cpcon, &lfcon))
154 return -1;
155 scratch2.pllm_base_divm = divm;
156 scratch2.pllm_base_divn = divn;
157 scratch2.pllm_base_divp = divp;
158 scratch2.pllm_misc_cpcon = cpcon;
159 scratch2.pllm_misc_lfcon = lfcon;
160 }
161
162 scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
163 scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
164 scratch2.memory_type = sdram.memory_type;
165 writel(scratch2.word, &pmc->pmc_scratch2);
166
167 /* collect data from various sources for pmc_scratch4 */
168 fbio_spare.word = readl(&emc->fbio_spare);
169 scratch4.word = 0;
170 scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
171 scratch4.emc_clock_divider = sdram.emc_clock_divider;
172 scratch4.pllm_stable_time = -1;
173 scratch4.pllx_stable_time = -1;
174 writel(scratch4.word, &pmc->pmc_scratch4);
175
176 /* collect various data from sdram for pmc_scratch24 */
177 scratch24.word = 0;
178 scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
179 scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
180 scratch24.warmboot_wait = sdram.warm_boot_wait;
181 writel(scratch24.word, &pmc->pmc_scratch24);
182
183 return 0;
184 }
185
get_major_version(void)186 static u32 get_major_version(void)
187 {
188 u32 major_id;
189 struct apb_misc_gp_ctlr *gp =
190 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
191
192 major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
193 HIDREV_MAJORPREV_SHIFT;
194 return major_id;
195 }
196
is_production_mode_fuse_set(struct fuse_regs * fuse)197 static int is_production_mode_fuse_set(struct fuse_regs *fuse)
198 {
199 return readl(&fuse->production_mode);
200 }
201
is_odm_production_mode_fuse_set(struct fuse_regs * fuse)202 static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
203 {
204 return readl(&fuse->security_mode);
205 }
206
is_failure_analysis_mode(struct fuse_regs * fuse)207 static int is_failure_analysis_mode(struct fuse_regs *fuse)
208 {
209 return readl(&fuse->fa);
210 }
211
ap20_is_odm_production_mode(void)212 static int ap20_is_odm_production_mode(void)
213 {
214 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
215
216 if (!is_failure_analysis_mode(fuse) &&
217 is_odm_production_mode_fuse_set(fuse))
218 return 1;
219 else
220 return 0;
221 }
222
ap20_is_production_mode(void)223 static int ap20_is_production_mode(void)
224 {
225 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
226
227 if (get_major_version() == 0)
228 return 1;
229
230 if (!is_failure_analysis_mode(fuse) &&
231 is_production_mode_fuse_set(fuse) &&
232 !is_odm_production_mode_fuse_set(fuse))
233 return 1;
234 else
235 return 0;
236 }
237
fuse_get_operation_mode(void)238 static enum fuse_operating_mode fuse_get_operation_mode(void)
239 {
240 u32 chip_id;
241 struct apb_misc_gp_ctlr *gp =
242 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
243
244 chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
245 HIDREV_CHIPID_SHIFT;
246 if (chip_id == CHIPID_TEGRA20) {
247 if (ap20_is_odm_production_mode()) {
248 printf("!! odm_production_mode is not supported !!\n");
249 return MODE_UNDEFINED;
250 } else
251 if (ap20_is_production_mode())
252 return MODE_PRODUCTION;
253 else
254 return MODE_UNDEFINED;
255 }
256 return MODE_UNDEFINED;
257 }
258
determine_crypto_options(int * is_encrypted,int * is_signed,int * use_zero_key)259 static void determine_crypto_options(int *is_encrypted, int *is_signed,
260 int *use_zero_key)
261 {
262 switch (fuse_get_operation_mode()) {
263 case MODE_PRODUCTION:
264 *is_encrypted = 0;
265 *is_signed = 1;
266 *use_zero_key = 1;
267 break;
268 case MODE_UNDEFINED:
269 default:
270 *is_encrypted = 0;
271 *is_signed = 0;
272 *use_zero_key = 0;
273 break;
274 }
275 }
276
sign_wb_code(u32 start,u32 length,int use_zero_key)277 static int sign_wb_code(u32 start, u32 length, int use_zero_key)
278 {
279 int err;
280 u8 *source; /* Pointer to source */
281 u8 *hash;
282
283 /* Calculate AES block parameters. */
284 source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
285 length -= offsetof(struct wb_header, random_aes_block);
286 hash = (u8 *)(start + offsetof(struct wb_header, hash));
287 err = sign_data_block(source, length, hash);
288
289 return err;
290 }
291
warmboot_prepare_code(u32 seg_address,u32 seg_length)292 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
293 {
294 int err = 0;
295 u32 length; /* length of the signed/encrypt code */
296 struct wb_header *dst_header; /* Pointer to dest WB header */
297 int is_encrypted; /* Segment is encrypted */
298 int is_signed; /* Segment is signed */
299 int use_zero_key; /* Use key of all zeros */
300
301 /* Determine crypto options. */
302 determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
303
304 /* Get the actual code limits. */
305 length = roundup(((u32)wb_end - (u32)wb_start), 16);
306
307 /*
308 * The region specified by seg_address must be in SDRAM and must be
309 * nonzero in length.
310 */
311 if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
312 seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
313 err = -EFAULT;
314 goto fail;
315 }
316
317 /* Things must be 16-byte aligned. */
318 if ((seg_length & 0xF) || (seg_address & 0xF)) {
319 err = -EINVAL;
320 goto fail;
321 }
322
323 /* Will the code fit? (destination includes wb_header + wb code) */
324 if (seg_length < (length + sizeof(struct wb_header))) {
325 err = -EINVAL;
326 goto fail;
327 }
328
329 dst_header = (struct wb_header *)seg_address;
330 memset((char *)dst_header, 0, sizeof(struct wb_header));
331
332 /* Populate the random_aes_block as requested. */
333 {
334 u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
335 u32 *end = (u32 *)(((u32)aes_block) +
336 sizeof(dst_header->random_aes_block));
337
338 do {
339 *aes_block++ = 0;
340 } while (aes_block < end);
341 }
342
343 /* Populate the header. */
344 dst_header->length_insecure = length + sizeof(struct wb_header);
345 dst_header->length_secure = length + sizeof(struct wb_header);
346 dst_header->destination = NV_WB_RUN_ADDRESS;
347 dst_header->entry_point = NV_WB_RUN_ADDRESS;
348 dst_header->code_length = length;
349
350 if (is_encrypted) {
351 printf("!!!! Encryption is not supported !!!!\n");
352 dst_header->length_insecure = 0;
353 err = -EACCES;
354 goto fail;
355 } else
356 /* copy the wb code directly following dst_header. */
357 memcpy((char *)(dst_header+1), (char *)wb_start, length);
358
359 if (is_signed)
360 err = sign_wb_code(seg_address, dst_header->length_insecure,
361 use_zero_key);
362
363 fail:
364 if (err)
365 printf("Warning: warmboot code copy failed (error=%d)\n", err);
366
367 return err;
368 }
369