1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/flow.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/tegra_i2c.h>
15 #include <linux/delay.h>
16 #include "../cpu.h"
17
18 /* In case this function is not defined */
pmic_enable_cpu_vdd(void)19 __weak void pmic_enable_cpu_vdd(void) {}
20
enable_cpu_power_rail(void)21 static void enable_cpu_power_rail(void)
22 {
23 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
24 u32 reg;
25
26 debug("enable_cpu_power_rail entry\n");
27 reg = readl(&pmc->pmc_cntrl);
28 reg |= CPUPWRREQ_OE;
29 writel(reg, &pmc->pmc_cntrl);
30 }
31
32 /**
33 * The T30 requires some special clock initialization, including setting up
34 * the dvc i2c, turning on mselect and selecting the G CPU cluster
35 */
t30_init_clocks(void)36 void t30_init_clocks(void)
37 {
38 struct clk_rst_ctlr *clkrst =
39 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
40 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
41 u32 val;
42
43 debug("t30_init_clocks entry\n");
44 /* Set active CPU cluster to G */
45 clrbits_le32(flow->cluster_control, 1 << 0);
46
47 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
48
49 val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
50 (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
51 (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
52 (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
53 writel(val, &clkrst->crc_clk_sys_rate);
54
55 /* Put i2c, mselect in reset and enable clocks */
56 reset_set_enable(PERIPH_ID_DVC_I2C, 1);
57 clock_set_enable(PERIPH_ID_DVC_I2C, 1);
58 reset_set_enable(PERIPH_ID_MSELECT, 1);
59 clock_set_enable(PERIPH_ID_MSELECT, 1);
60
61 /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
62 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
63
64 /*
65 * Our high-level clock routines are not available prior to
66 * relocation. We use the low-level functions which require a
67 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
68 */
69 clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
70
71 /*
72 * Give clocks time to stabilize, then take i2c and mselect out of
73 * reset
74 */
75 udelay(1000);
76 reset_set_enable(PERIPH_ID_DVC_I2C, 0);
77 reset_set_enable(PERIPH_ID_MSELECT, 0);
78 }
79
set_cpu_running(int run)80 static void set_cpu_running(int run)
81 {
82 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
83
84 debug("set_cpu_running entry, run = %d\n", run);
85 writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
86 }
87
start_cpu(u32 reset_vector)88 void start_cpu(u32 reset_vector)
89 {
90 debug("start_cpu entry, reset_vector = %x\n", reset_vector);
91 t30_init_clocks();
92
93 /* Enable VDD_CPU */
94 enable_cpu_power_rail();
95 pmic_enable_cpu_vdd();
96
97 set_cpu_running(0);
98
99 /* Hold the CPUs in reset */
100 reset_A9_cpu(1);
101
102 /* Disable the CPU clock */
103 enable_cpu_clock(0);
104
105 /* Enable CoreSight */
106 clock_enable_coresight(1);
107
108 /*
109 * Set the entry point for CPU execution from reset,
110 * if it's a non-zero value.
111 */
112 if (reset_vector)
113 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
114
115 /* Enable the CPU clock */
116 enable_cpu_clock(1);
117
118 /* If the CPU doesn't already have power, power it up */
119 powerup_cpu();
120
121 /* Take the CPU out of reset */
122 reset_A9_cpu(0);
123
124 set_cpu_running(1);
125 }
126