1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 - 2022, Xilinx, Inc.
4 * Copyright (C) 2022, Advanced Micro Devices, Inc.
5 *
6 * Michal Simek <michal.simek@amd.com>
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <asm/armv8/mmu.h>
12 #include <asm/cache.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/cache.h>
18 #include <dm/platdata.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #define VERSAL_NET_MEM_MAP_USED 5
23
24 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
25
26 /* +1 is end of list which needs to be empty */
27 #define VERSAL_NET_MEM_MAP_MAX (VERSAL_NET_MEM_MAP_USED + DRAM_BANKS + 1)
28
29 static struct mm_region versal_mem_map[VERSAL_NET_MEM_MAP_MAX] = {
30 {
31 .virt = 0x80000000UL,
32 .phys = 0x80000000UL,
33 .size = 0x70000000UL,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_NON_SHARE |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN
37 }, {
38 .virt = 0xf0000000UL,
39 .phys = 0xf0000000UL,
40 .size = 0x0fe00000UL,
41 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
42 PTE_BLOCK_NON_SHARE |
43 PTE_BLOCK_PXN | PTE_BLOCK_UXN
44 }, {
45 .virt = 0x400000000UL,
46 .phys = 0x400000000UL,
47 .size = 0x200000000UL,
48 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
49 PTE_BLOCK_NON_SHARE |
50 PTE_BLOCK_PXN | PTE_BLOCK_UXN
51 }, {
52 .virt = 0x600000000UL,
53 .phys = 0x600000000UL,
54 .size = 0x800000000UL,
55 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
56 PTE_BLOCK_INNER_SHARE
57 }, {
58 .virt = 0xe00000000UL,
59 .phys = 0xe00000000UL,
60 .size = 0xf200000000UL,
61 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
62 PTE_BLOCK_NON_SHARE |
63 PTE_BLOCK_PXN | PTE_BLOCK_UXN
64 }
65 };
66
mem_map_fill(void)67 void mem_map_fill(void)
68 {
69 int banks = VERSAL_NET_MEM_MAP_USED;
70
71 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
72 /* Zero size means no more DDR that's this is end */
73 if (!gd->bd->bi_dram[i].size)
74 break;
75
76 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
77 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
78 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
79 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
80 PTE_BLOCK_INNER_SHARE;
81 banks = banks + 1;
82 }
83 }
84
85 struct mm_region *mem_map = versal_mem_map;
86
get_page_table_size(void)87 u64 get_page_table_size(void)
88 {
89 return 0x14000;
90 }
91
92 U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
93 .name = "soc_xilinx_versal_net",
94 };
95