1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
5 */
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <zynqpl.h>
10 #include <asm/cache.h>
11 #include <asm/io.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/ps7_init_gpl.h>
15 #include <asm/arch/sys_proto.h>
16
17 #define ZYNQ_SILICON_VER_MASK 0xF0000000
18 #define ZYNQ_SILICON_VER_SHIFT 28
19
20 #if CONFIG_IS_ENABLED(FPGA)
21 xilinx_desc fpga = {
22 .family = xilinx_zynq,
23 .iface = devcfg,
24 .operations = &zynq_op,
25 .flags = FPGA_LEGACY,
26 };
27 #endif
28
29 static const struct {
30 u8 idcode;
31 #if defined(CONFIG_FPGA)
32 u32 fpga_size;
33 #endif
34 char *devicename;
35 } zynq_fpga_descs[] = {
36 ZYNQ_DESC(7Z007S),
37 ZYNQ_DESC(7Z010),
38 ZYNQ_DESC(7Z012S),
39 ZYNQ_DESC(7Z014S),
40 ZYNQ_DESC(7Z015),
41 ZYNQ_DESC(7Z020),
42 ZYNQ_DESC(7Z030),
43 ZYNQ_DESC(7Z035),
44 ZYNQ_DESC(7Z045),
45 ZYNQ_DESC(7Z100),
46 { /* Sentinel */ },
47 };
48
arch_cpu_init(void)49 int arch_cpu_init(void)
50 {
51 zynq_slcr_unlock();
52 #ifndef CONFIG_SPL_BUILD
53 /* Device config APB, unlock the PCAP */
54 writel(0x757BDF0D, &devcfg_base->unlock);
55 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
56
57 #if (CFG_SYS_SDRAM_BASE == 0)
58 /* remap DDR to zero, FILTERSTART */
59 writel(0, &scu_base->filter_start);
60
61 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
62 writel(0x1F, &slcr_base->ocm_cfg);
63 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
64 writel(0x0, &slcr_base->fpga_rst_ctrl);
65 /* Set urgent bits with register */
66 writel(0x0, &slcr_base->ddr_urgent_sel);
67 /* Urgent write, ports S2/S3 */
68 writel(0xC, &slcr_base->ddr_urgent);
69 #endif
70 #endif
71 zynq_slcr_lock();
72
73 return 0;
74 }
75
zynq_get_silicon_version(void)76 unsigned int zynq_get_silicon_version(void)
77 {
78 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
79 >> ZYNQ_SILICON_VER_SHIFT;
80 }
81
reset_cpu(void)82 void reset_cpu(void)
83 {
84 zynq_slcr_cpu_reset();
85 while (1)
86 ;
87 }
88
89 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
enable_caches(void)90 void enable_caches(void)
91 {
92 /* Enable D-cache. I-cache is already enabled in start.S */
93 dcache_enable();
94 }
95 #endif
96
cpu_desc_id(void)97 static int __maybe_unused cpu_desc_id(void)
98 {
99 u32 idcode;
100 u8 i;
101
102 idcode = zynq_slcr_get_idcode();
103 for (i = 0; zynq_fpga_descs[i].idcode; i++) {
104 if (zynq_fpga_descs[i].idcode == idcode)
105 return i;
106 }
107
108 return -ENODEV;
109 }
110
111 #if defined(CONFIG_ARCH_EARLY_INIT_R)
arch_early_init_r(void)112 int arch_early_init_r(void)
113 {
114 #if CONFIG_IS_ENABLED(FPGA)
115 int cpu_id = cpu_desc_id();
116
117 if (cpu_id < 0)
118 return 0;
119
120 fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
121 fpga.name = zynq_fpga_descs[cpu_id].devicename;
122 fpga_init();
123 fpga_add(fpga_xilinx, &fpga);
124 #endif
125 return 0;
126 }
127 #endif
128
129 #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)130 int print_cpuinfo(void)
131 {
132 u32 version;
133 int cpu_id = cpu_desc_id();
134
135 if (cpu_id < 0)
136 return 0;
137
138 version = zynq_get_silicon_version() << 1;
139 if (version > (PCW_SILICON_VERSION_3 << 1))
140 version += 1;
141
142 printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
143 printf("Silicon: v%d.%d\n", version >> 1, version & 1);
144 return 0;
145 }
146 #endif
147