1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
4  */
5 #include <common.h>
6 #include <debug_uart.h>
7 #include <hang.h>
8 #include <image.h>
9 #include <init.h>
10 #include <log.h>
11 #include <spl.h>
12 
13 #include <asm/io.h>
14 #include <asm/spl.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/ps7_init_gpl.h>
18 
19 #if defined(CONFIG_DEBUG_UART_BOARD_INIT)
board_debug_uart_init(void)20 void board_debug_uart_init(void)
21 {
22 	ps7_init();
23 }
24 #endif
25 
board_init_f(ulong dummy)26 void board_init_f(ulong dummy)
27 {
28 #if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
29 	ps7_init();
30 #endif
31 
32 	arch_cpu_init();
33 }
34 
35 #ifdef CONFIG_SPL_BOARD_INIT
spl_board_init(void)36 void spl_board_init(void)
37 {
38 	preloader_console_init();
39 #if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
40 	arch_early_init_r();
41 #endif
42 	board_init();
43 }
44 #endif
45 
spl_boot_device(void)46 u32 spl_boot_device(void)
47 {
48 	u32 mode;
49 
50 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
51 #ifdef CONFIG_SPL_SPI
52 	case ZYNQ_BM_QSPI:
53 		mode = BOOT_DEVICE_SPI;
54 		break;
55 #endif
56 	case ZYNQ_BM_NAND:
57 		mode = BOOT_DEVICE_NAND;
58 		break;
59 	case ZYNQ_BM_NOR:
60 		mode = BOOT_DEVICE_NOR;
61 		break;
62 #ifdef CONFIG_SPL_MMC
63 	case ZYNQ_BM_SD:
64 		mode = BOOT_DEVICE_MMC1;
65 		break;
66 #endif
67 	case ZYNQ_BM_JTAG:
68 		mode = BOOT_DEVICE_RAM;
69 		break;
70 	default:
71 		puts("Unsupported boot mode selected\n");
72 		hang();
73 	}
74 
75 	return mode;
76 }
77 
78 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)79 int spl_start_uboot(void)
80 {
81 	/* boot linux */
82 	return 0;
83 }
84 #endif
85 
spl_board_prepare_for_boot(void)86 void spl_board_prepare_for_boot(void)
87 {
88 	ps7_post_config();
89 	debug("SPL bye\n");
90 }
91