1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Nuvoton Technology Corp. 4 * 5 * Device Tree binding constants for NPCM8XX clock controller. 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H 9 #define __DT_BINDINGS_CLOCK_NPCM8XX_H 10 11 #define NPCM8XX_CLK_CPU 0 12 #define NPCM8XX_CLK_GFX_PIXEL 1 13 #define NPCM8XX_CLK_MC 2 14 #define NPCM8XX_CLK_ADC 3 15 #define NPCM8XX_CLK_AHB 4 16 #define NPCM8XX_CLK_TIMER 5 17 #define NPCM8XX_CLK_UART 6 18 #define NPCM8XX_CLK_UART2 7 19 #define NPCM8XX_CLK_MMC 8 20 #define NPCM8XX_CLK_SPI3 9 21 #define NPCM8XX_CLK_PCI 10 22 #define NPCM8XX_CLK_AXI 11 23 #define NPCM8XX_CLK_APB4 12 24 #define NPCM8XX_CLK_APB3 13 25 #define NPCM8XX_CLK_APB2 14 26 #define NPCM8XX_CLK_APB1 15 27 #define NPCM8XX_CLK_APB5 16 28 #define NPCM8XX_CLK_CLKOUT 17 29 #define NPCM8XX_CLK_GFX 18 30 #define NPCM8XX_CLK_SU 19 31 #define NPCM8XX_CLK_SU48 20 32 #define NPCM8XX_CLK_SDHC 21 33 #define NPCM8XX_CLK_SPI0 22 34 #define NPCM8XX_CLK_SPI1 23 35 #define NPCM8XX_CLK_SPIX 24 36 #define NPCM8XX_CLK_RG 25 37 #define NPCM8XX_CLK_RCP 26 38 #define NPCM8XX_CLK_PRE_ADC 27 39 #define NPCM8XX_CLK_ATB 28 40 #define NPCM8XX_CLK_PRE_CLK 29 41 #define NPCM8XX_CLK_TH 30 42 #define NPCM8XX_CLK_REFCLK 31 43 #define NPCM8XX_CLK_SYSBYPCK 32 44 #define NPCM8XX_CLK_MCBYPCK 33 45 #define NPCM8XX_CLK_PLL0 34 46 #define NPCM8XX_CLK_PLL1 35 47 #define NPCM8XX_CLK_PLL2 36 48 #define NPCM8XX_CLK_PLL2DIV2 37 49 50 #define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_PLL2DIV2 + 1) 51 52 #endif 53