1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt7621-clk.h>
9#include <dt-bindings/reset/mt7621-reset.h>
10#include <dt-bindings/phy/phy.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	compatible = "mediatek,mt7621-soc";
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "mips,mips1004Kc";
24			reg = <0>;
25		};
26
27		cpu@1 {
28			device_type = "cpu";
29			compatible = "mips,mips1004Kc";
30			reg = <1>;
31		};
32	};
33
34	clk48m: clk48m {
35		compatible = "fixed-clock";
36
37		clock-frequency = <48000000>;
38
39		#clock-cells = <0>;
40	};
41
42	clk50m: clk50m {
43		compatible = "fixed-clock";
44
45		clock-frequency = <50000000>;
46
47		#clock-cells = <0>;
48	};
49
50	sysc: sysctrl@1e000000 {
51		compatible = "mediatek,mt7621-sysc", "syscon";
52		reg = <0x1e000000 0x100>;
53
54		clkctrl: clock-controller@1e000030 {
55			compatible = "mediatek,mt7621-clk";
56			mediatek,memc = <&memc>;
57
58			#clock-cells = <1>;
59		};
60	};
61
62	rstctrl: reset-controller@1e000034 {
63		compatible = "mediatek,mtmips-reset";
64		reg = <0x1e000034 0x4>;
65		#reset-cells = <1>;
66	};
67
68	reboot: resetctl-reboot {
69		compatible = "resetctl-reboot";
70
71		resets = <&rstctrl RST_SYS>;
72		reset-names = "sysreset";
73	};
74
75	memc: memctrl@1e005000 {
76		compatible = "mediatek,mt7621-memc", "syscon";
77		reg = <0x1e005000 0x1000>;
78	};
79
80	pinctrl: pinctrl@1e000060 {
81		compatible = "mediatek,mt7621-pinctrl";
82		reg = <0x1e000048 0x30>;
83
84		pinctrl-names = "default";
85		pinctrl-0 = <&state_default>;
86
87		state_default: pin_state {
88		};
89
90		uart1_pins: uart1_pins {
91			groups = "uart1";
92			function = "uart";
93		};
94
95		uart2_pins: uart2_pins {
96			groups = "uart2";
97			function = "uart";
98		};
99
100		uart3_pins: uart3_pins {
101			groups = "uart3";
102			function = "uart";
103		};
104
105		sdxc_pins: sdxc_pins {
106			groups = "sdxc";
107			function = "sdxc";
108		};
109
110		spi_pins: spi_pins {
111			groups = "spi";
112			function = "spi";
113		};
114
115		eth_pins: eth_pins {
116			mdio_pins {
117				groups = "mdio";
118				function = "mdio";
119			};
120
121			rgmii1_pins {
122				groups = "rgmii1";
123				function = "rgmii";
124			};
125
126			esw_pins {
127				groups = "esw int";
128				function = "esw int";
129			};
130
131			mdio_pconf {
132				groups = "mdio";
133				drive-strength = <2>;
134			};
135		};
136	};
137
138	watchdog: watchdog@1e000100 {
139		compatible = "mediatek,mt7621-wdt";
140		reg = <0x1e000100 0x40>;
141
142		resets = <&rstctrl RST_TIMER>;
143		reset-names = "wdt";
144
145		status = "disabled";
146	};
147
148	gpio: gpio@1e000600 {
149		#address-cells = <1>;
150		#size-cells = <0>;
151
152		compatible = "mtk,mt7621-gpio";
153		reg = <0x1e000600 0x100>;
154
155		resets = <&rstctrl RST_PIO>;
156		reset-names = "pio";
157
158		gpio0: bank@0 {
159			reg = <0>;
160			compatible = "mtk,mt7621-gpio-bank";
161			gpio-controller;
162			#gpio-cells = <2>;
163		};
164
165		gpio1: bank@1 {
166			reg = <1>;
167			compatible = "mtk,mt7621-gpio-bank";
168			gpio-controller;
169			#gpio-cells = <2>;
170		};
171
172		gpio2: bank@2 {
173			reg = <2>;
174			compatible = "mtk,mt7621-gpio-bank";
175			gpio-controller;
176			#gpio-cells = <2>;
177		};
178	};
179
180	spi: spi@1e000b00 {
181		compatible = "ralink,mt7621-spi";
182		reg = <0x1e000b00 0x40>;
183
184		status = "disabled";
185
186		pinctrl-names = "default";
187		pinctrl-0 = <&spi_pins>;
188
189		resets = <&rstctrl RST_SPI>;
190		reset-names = "spi";
191
192		clocks = <&clkctrl MT7621_CLK_SPI>;
193
194		#address-cells = <1>;
195		#size-cells = <0>;
196	};
197
198	uart0: uart1@1e000c00 {
199		compatible = "mediatek,hsuart", "ns16550a";
200		reg = <0x1e000c00 0x100>;
201
202		pinctrl-names = "default";
203		pinctrl-0 = <&uart1_pins>;
204
205		clocks = <&clkctrl MT7621_CLK_UART1>;
206
207		resets = <&rstctrl RST_UART1>;
208
209		reg-shift = <2>;
210	};
211
212	uart1: uart2@1e000d00 {
213		compatible = "mediatek,hsuart", "ns16550a";
214		reg = <0x1e000d00 0x100>;
215
216		pinctrl-names = "default";
217		pinctrl-0 = <&uart2_pins>;
218
219		clocks = <&clkctrl MT7621_CLK_UART2>;
220
221		resets = <&rstctrl RST_UART2>;
222
223		reg-shift = <2>;
224
225		status = "disabled";
226	};
227
228	uart2: uart3@1e000e00 {
229		compatible = "mediatek,hsuart", "ns16550a";
230		reg = <0x1e000e00 0x100>;
231
232		pinctrl-names = "default";
233		pinctrl-0 = <&uart3_pins>;
234
235		clocks = <&clkctrl MT7621_CLK_UART3>;
236
237		resets = <&rstctrl RST_UART3>;
238
239		reg-shift = <2>;
240
241		status = "disabled";
242	};
243
244	eth: eth@1e100000 {
245		compatible = "mediatek,mt7621-eth";
246		reg = <0x1e100000 0x20000>;
247		mediatek,ethsys = <&sysc>;
248
249		pinctrl-names = "default";
250		pinctrl-0 = <&eth_pins>;
251
252		resets = <&rstctrl RST_FE>, <&rstctrl RST_GMAC>, <&rstctrl RST_MCM>;
253		reset-names = "fe", "gmac", "mcm";
254
255		clocks = <&clkctrl MT7621_CLK_GDMA>,
256			 <&clkctrl MT7621_CLK_ETH>;
257		clock-names = "gmac", "fe";
258
259		#address-cells = <1>;
260		#size-cells = <0>;
261
262		mediatek,gmac-id = <0>;
263		phy-mode = "rgmii";
264		mediatek,switch = "mt7530";
265		mediatek,mcm;
266
267		fixed-link {
268			speed = <1000>;
269			full-duplex;
270		};
271	};
272
273	mmc: mmc@1e130000 {
274		compatible = "mediatek,mt7621-mmc";
275		reg = <0x1e130000 0x4000>;
276
277		status = "disabled";
278
279		bus-width = <4>;
280		builtin-cd = <1>;
281		r_smpl = <1>;
282
283		pinctrl-names = "default";
284		pinctrl-0 = <&sdxc_pins>;
285
286		clocks = <&clk50m>, <&clkctrl MT7621_CLK_SHXC>;
287		clock-names = "source", "hclk";
288
289		resets = <&rstctrl RST_SDXC>;
290	};
291
292	ssusb: usb@1e1c0000 {
293		compatible = "mediatek,mt7621-xhci", "mediatek,mtk-xhci";
294		reg = <0x1e1c0000 0x1000>, <0x1e1d0700 0x100>;
295		reg-names = "mac", "ippc";
296
297		clocks = <&clk48m>, <&clk48m>;
298		clock-names = "sys_ck", "ref_ck";
299
300		phys = <&u2port0 PHY_TYPE_USB2>,
301		       <&u3port0 PHY_TYPE_USB3>,
302		       <&u2port1 PHY_TYPE_USB2>;
303
304		status = "disabled";
305	};
306
307	u3phy: usb-phy@1e1d0000 {
308		compatible = "mediatek,mt7621-u3phy",
309			     "mediatek,generic-tphy-v1";
310		reg = <0x1e1d0000 0x700>;
311		#address-cells = <1>;
312		#size-cells = <1>;
313		ranges;
314		status = "disabled";
315
316		u2port0: usb-phy@1e1d0800 {
317			reg = <0x1e1d0800 0x0100>;
318			#phy-cells = <1>;
319			clocks = <&clk48m>;
320			clock-names = "ref";
321		};
322
323		u3port0: usb-phy@1e1d0900 {
324			reg = <0x1e1d0900 0x0100>;
325			#phy-cells = <1>;
326		};
327
328		u2port1: usb-phy@1e1d1000 {
329			reg = <0x1e1d1000 0x0100>;
330			#phy-cells = <1>;
331			clocks = <&clk48m>;
332			clock-names = "ref";
333		};
334	};
335
336	i2c: i2c@1e000900 {
337		compatible = "i2c-gpio";
338
339		status = "disabled";
340
341		i2c-gpio,delay-us = <3>;
342
343		gpios = <&gpio0 3 1>, /* PIN3 as SDA */
344			<&gpio0 4 1>; /* PIN4 as CLK */
345
346		#address-cells = <1>;
347		#size-cells = <0>;
348	};
349};
350