1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. All rights reserved. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8 #ifndef _MT7621_H_ 9 #define _MT7621_H_ 10 11 #define SYSCTL_BASE 0x1e000000 12 #define SYSCTL_SIZE 0x100 13 #define TIMER_BASE 0x1e000100 14 #define TIMER_SIZE 0x100 15 #define RBUS_BASE 0x1e000400 16 #define RBUS_SIZE 0x100 17 #define GPIO_BASE 0x1e000600 18 #define GPIO_SIZE 0x100 19 #define DMA_CFG_ARB_BASE 0x1e000800 20 #define DMA_CFG_ARB_SIZE 0x100 21 #define SPI_BASE 0x1e000b00 22 #define SPI_SIZE 0x100 23 #define UART1_BASE 0x1e000c00 24 #define UART1_SIZE 0x100 25 #define UART2_BASE 0x1e000d00 26 #define UART2_SIZE 0x100 27 #define UART3_BASE 0x1e000e00 28 #define UART3_SIZE 0x100 29 #define NFI_BASE 0x1e003000 30 #define NFI_SIZE 0x800 31 #define NFI_ECC_BASE 0x1e003800 32 #define NFI_ECC_SIZE 0x800 33 #define DRAMC_BASE 0x1e005000 34 #define DRAMC_SIZE 0x1000 35 #define FE_BASE 0x1e100000 36 #define FE_SIZE 0xe000 37 #define GMAC_BASE 0x1e110000 38 #define GMAC_SIZE 0x8000 39 #define SSUSB_BASE 0x1e1c0000 40 #define SSUSB_SIZE 0x40000 41 42 /* GIC Base Address */ 43 #define MIPS_GIC_BASE 0x1fbc0000 44 45 /* CPC Base Address */ 46 #define MIPS_CPC_BASE 0x1fbf0000 47 48 /* Flash Memory-mapped Base Address */ 49 #define FLASH_MMAP_BASE 0x1fc00000 50 #define TPL_INFO_OFFSET 0x40 51 #define TPL_INFO_MAGIC 0x31323637 /* Magic "7621" */ 52 53 /* SRAM */ 54 #define FE_SRAM_BASE1 0x8000 55 #define FE_SRAM_BASE2 0xa000 56 57 /* SYSCTL_BASE */ 58 #define SYSCTL_CHIP_REV_ID_REG 0x0c 59 #define CPU_ID 0x20000 60 #define PKG_ID 0x10000 61 #define VER_ID_S 8 62 #define VER_ID_M 0xf00 63 #define ECO_ID_S 0 64 #define ECO_ID_M 0x0f 65 66 #define SYSCTL_SYSCFG0_REG 0x10 67 #define XTAL_MODE_SEL_S 6 68 #define XTAL_MODE_SEL_M 0x1c0 69 #define DRAM_TYPE 0x10 70 #define CHIP_MODE_S 0 71 #define CHIP_MODE_M 0x0f 72 73 #define BOOT_SRAM_BASE_REG 0x20 74 75 #define SYSCTL_CLKCFG0_REG 0x2c 76 #define CPU_CLK_SEL_S 30 77 #define CPU_CLK_SEL_M 0xc0000000 78 #define MPLL_CFG_SEL_S 23 79 #define MPLL_CFG_SEL_M 0x800000 80 81 #define SYSCTL_RSTCTL_REG 0x34 82 #define MCM_RST 0x04 83 #define SYS_RST 0x01 84 85 #define SYSCTL_CUR_CLK_STS_REG 0x44 86 #define CUR_CPU_FDIV_S 8 87 #define CUR_CPU_FDIV_M 0x1f00 88 #define CUR_CPU_FFRAC_S 0 89 #define CUR_CPU_FFRAC_M 0x1f 90 91 #define SYSCTL_GPIOMODE_REG 0x60 92 #define UART2_MODE_S 5 93 #define UART2_MODE_M 0x60 94 #define UART3_MODE_S 3 95 #define UART3_MODE_M 0x18 96 #define UART1_MODE 0x02 97 98 /* RBUS_BASE */ 99 #define RBUS_DYN_CFG0_REG 0x0010 100 #define CPU_FDIV_S 8 101 #define CPU_FDIV_M 0x1f00 102 #define CPU_FFRAC_S 0 103 #define CPU_FFRAC_M 0x1f 104 105 /* DMA_CFG_ARB_BASE */ 106 #define DMA_ROUTE_REG 0x000c 107 108 /* SPI_BASE */ 109 #define SPI_SPACE_REG 0x003c 110 #define FS_SLAVE_SEL_S 12 111 #define FS_SLAVE_SEL_M 0x70000 112 #define FS_CLK_SEL_S 0 113 #define FS_CLK_SEL_M 0xfff 114 115 /* FE_BASE */ 116 #define FE_RST_GLO_REG 0x0004 117 #define FE_PSE_RAM 0x04 118 #define FE_PSE_MEM_EN 0x02 119 #define FE_PSE_RESET 0x01 120 121 /* SSUSB_BASE */ 122 #define SSUSB_MAC_CK_CTRL_REG 0x10784 123 #define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_S 16 124 #define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M 0xff0000 125 #define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_S 8 126 #define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M 0xff00 127 #define SSUSB_MAC3_SYS_CK_GATE_MODE_S 2 128 #define SSUSB_MAC3_SYS_CK_GATE_MODE_M 0x0c 129 #define SSUSB_MAC2_SYS_CK_GATE_MODE_S 0 130 #define SSUSB_MAC2_SYS_CK_GATE_MODE_M 0x03 131 132 #define SSUSB_B2_ROSC_0_REG 0x10a40 133 #define SSUSB_RING_OSC_CNTEND_S 23 134 #define SSUSB_RING_OSC_CNTEND_M 0xff800000 135 #define SSUSB_XTAL_OSC_CNTEND_S 16 136 #define SSUSB_XTAL_OSC_CNTEND_M 0x7f0000 137 #define SSUSB_RING_BYPASS_DET 0x01 138 139 #define SSUSB_B2_ROSC_1_REG 0x10a44 140 #define SSUSB_RING_OSC_FRC_RECAL_S 17 141 #define SSUSB_RING_OSC_FRC_RECAL_M 0x60000 142 #define SSUSB_RING_OSC_FRC_SEL 0x01 143 144 #define SSUSB_U3PHYA_1_REG 0x10b04 145 #define SSUSB_PCIE_CLKDRV_AMP_S 27 146 #define SSUSB_PCIE_CLKDRV_AMP_M 0x38000000 147 #define SSUSB_SYSPLL_FBSEL_S 2 148 #define SSUSB_SYSPLL_FBSEL_M 0x0c 149 #define SSUSB_SYSPLL_PREDIV_S 0 150 #define SSUSB_SYSPLL_PREDIV_M 0x03 151 152 #define SSUSB_U3PHYA_2_REG 0x10b08 153 #define SSUSB_SYSPLL_FBDIV_S 24 154 #define SSUSB_SYSPLL_FBDIV_M 0x7f000000 155 #define SSUSB_SYSPLL_VCO_DIV_SEL 0x200000 156 #define SSUSB_SYSPLL_FPEN 0x2000 157 #define SSUSB_SYSPLL_MONCK_EN 0x1000 158 #define SSUSB_SYSPLL_VOD_EN 0x200 159 160 #define SSUSB_U3PHYA_3_REG 0x10b10 161 #define SSUSB_SYSPLL_PCW_NCPO_S 1 162 #define SSUSB_SYSPLL_PCW_NCPO_M 0xfffffffe 163 164 #define SSUSB_U3PHYA_9_REG 0x10b24 165 #define SSUSB_PLL_SSC_PRD_S 0 166 #define SSUSB_PLL_SSC_PRD_M 0xffff 167 168 #define SSUSB_U3PHYA_11_REG 0x10b2c 169 #define SSUSB_EQ_CURSEL 0x1000000 170 #define SSUSB_RX_DAC_MUX_S 19 171 #define SSUSB_RX_DAC_MUX_M 0xf80000 172 #define SSUSB_PCIE_SIGDET_VTH_S 5 173 #define SSUSB_PCIE_SIGDET_VTH_M 0x60 174 #define SSUSB_PCIE_SIGDET_LPF_S 3 175 #define SSUSB_PCIE_SIGDET_LPF_M 0x18 176 177 #define DA_SSUSB_PLL_FBKDIV_REG 0x10c1c 178 #define SSUSB_PLL_FBKDIV_PE2H_S 24 179 #define SSUSB_PLL_FBKDIV_PE2H_M 0x7f000000 180 #define SSUSB_PLL_FBKDIV_PE1D_S 16 181 #define SSUSB_PLL_FBKDIV_PE1D_M 0x7f0000 182 #define SSUSB_PLL_FBKDIV_PE1H_S 8 183 #define SSUSB_PLL_FBKDIV_PE1H_M 0x7f00 184 #define SSUSB_PLL_FBKDIV_U3_S 0 185 #define SSUSB_PLL_FBKDIV_U3_M 0x7f 186 187 #define DA_SSUSB_U3PHYA_10_REG 0x10c20 188 #define SSUSB_PLL_PREDIV_PE1D_S 18 189 #define SSUSB_PLL_PREDIV_PE1D_M 0xc0000 190 #define SSUSB_PLL_PREDIV_U3_S 8 191 #define SSUSB_PLL_PREDIV_U3_M 0x300 192 #define SSUSB_PLL_FBKDI_S 0 193 #define SSUSB_PLL_FBKDI_M 0x07 194 195 #define DA_SSUSB_PLL_PCW_NCPO_REG 0x10c24 196 #define SSUSB_PLL_PCW_NCPO_U3_S 0 197 #define SSUSB_PLL_PCW_NCPO_U3_M 0x7fffffff 198 199 #define DA_SSUSB_PLL_SSC_DELTA1_REG 0x10c38 200 #define SSUSB_PLL_SSC_DELTA1_PE1H_S 16 201 #define SSUSB_PLL_SSC_DELTA1_PE1H_M 0xffff0000 202 #define SSUSB_PLL_SSC_DELTA1_U3_S 0 203 #define SSUSB_PLL_SSC_DELTA1_U3_M 0xffff 204 205 #define DA_SSUSB_U3PHYA_21_REG 0x10c40 206 #define SSUSB_PLL_SSC_DELTA_U3_S 16 207 #define SSUSB_PLL_SSC_DELTA_U3_M 0xffff0000 208 #define SSUSB_PLL_SSC_DELTA1_PE2D_S 0 209 #define SSUSB_PLL_SSC_DELTA1_PE2D_M 0xffff 210 211 /* MT7621 specific CM values */ 212 213 /* GCR_REGx_BASE */ 214 #define GCR_REG0_BASE_VALUE 0x1c000000 215 #define GCR_REG1_BASE_VALUE 0x60000000 216 #define GCR_REG2_BASE_VALUE 0x1c000000 217 #define GCR_REG3_BASE_VALUE 0x1c000000 218 219 /* GCR_REGx_MASK */ 220 #define GCR_REG0_MASK_VALUE 0x0000fc00 /* 64M Bus */ 221 #define GCR_REG1_MASK_VALUE 0x0000f000 /* 256M PCI Mem */ 222 #define GCR_REG2_MASK_VALUE 0x0000fc00 /* unused */ 223 #define GCR_REG3_MASK_VALUE 0x0000fc00 /* unused */ 224 225 #ifndef __ASSEMBLY__ 226 unsigned long get_xtal_mhz(void); 227 #endif 228 229 #endif /* _MT7621_H_ */ 230