1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
4 * Copyright (C) 2008-2009 MontaVista Software, Inc.
5 *
6 * Authors: Tony Li <tony.li@freescale.com>
7 * Anton Vorontsov <avorontsov@ru.mvista.com>
8 */
9
10 #include <common.h>
11 #include <clock_legacy.h>
12 #include <pci.h>
13 #include <mpc83xx.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <linux/delay.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define PCIE_MAX_BUSES 2
21
22 static struct {
23 u32 base;
24 u32 size;
25 } mpc83xx_pcie_cfg_space[] = {
26 {
27 .base = CFG_SYS_PCIE1_CFG_BASE,
28 .size = CFG_SYS_PCIE1_CFG_SIZE,
29 },
30 #if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE)
31 {
32 .base = CFG_SYS_PCIE2_CFG_BASE,
33 .size = CFG_SYS_PCIE2_CFG_SIZE,
34 },
35 #endif
36 };
37
get_pcie_clk(int index)38 int get_pcie_clk(int index)
39 {
40 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
41 u32 pci_sync_in;
42 u8 spmf;
43 u8 clkin_div;
44 u32 sccr;
45 u32 csb_clk;
46 u32 testval;
47
48 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
49 sccr = im->clk.sccr;
50 pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
51 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
52 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
53
54 if (index)
55 testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
56 else
57 testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
58
59 switch (testval) {
60 case 0:
61 return 0;
62 case 1:
63 return csb_clk;
64 case 2:
65 return csb_clk / 2;
66 case 3:
67 return csb_clk / 3;
68 }
69
70 return 0;
71 }
72
mpc83xx_pcie_init_bus(int bus,struct pci_region * reg)73 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
74 {
75 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
76 pex83xx_t *pex = &immr->pciexp[bus];
77 struct pex_outbound_window *out_win;
78 struct pex_inbound_window *in_win;
79 void *hose_cfg_base;
80 unsigned int ram_sz;
81 unsigned int barl;
82 unsigned int tar;
83 u16 reg16;
84 int i;
85
86 /* Enable pex csb bridge inbound & outbound transactions */
87 out_le32(&pex->bridge.pex_csb_ctrl,
88 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
89 PEX_CSB_CTRL_IBPIOE);
90
91 /* Enable bridge outbound */
92 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
93 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
94 PEX_CSB_OBCTRL_CFGWE);
95
96 out_win = &pex->bridge.pex_outbound_win[0];
97 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
98 mpc83xx_pcie_cfg_space[bus].size);
99 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
100 out_le32(&out_win->tarl, 0);
101 out_le32(&out_win->tarh, 0);
102
103 for (i = 0; i < 2; i++) {
104 u32 ar;
105
106 if (reg[i].size == 0)
107 break;
108
109 out_win = &pex->bridge.pex_outbound_win[i + 1];
110 out_le32(&out_win->bar, reg[i].phys_start);
111 out_le32(&out_win->tarl, reg[i].bus_start);
112 out_le32(&out_win->tarh, 0);
113 ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
114 if (reg[i].flags & PCI_REGION_IO)
115 ar |= PEX_OWAR_TYPE_IO;
116 else
117 ar |= PEX_OWAR_TYPE_MEM;
118 out_le32(&out_win->ar, ar);
119 }
120
121 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
122
123 ram_sz = gd->ram_size;
124 barl = 0;
125 tar = 0;
126 i = 0;
127 while (ram_sz > 0) {
128 in_win = &pex->bridge.pex_inbound_win[i];
129 out_le32(&in_win->barl, barl);
130 out_le32(&in_win->barh, 0x0);
131 out_le32(&in_win->tar, tar);
132 if (ram_sz >= 0x10000000) {
133 /* The maxium windows size is 256M */
134 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
135 PEX_IWAR_TYPE_PF | 0x0FFFF000);
136 barl += 0x10000000;
137 tar += 0x10000000;
138 ram_sz -= 0x10000000;
139 } else {
140 /* The UM is not clear here.
141 * So, round up to even Mb boundary */
142
143 ram_sz = ram_sz >> (20 +
144 ((ram_sz & 0xFFFFF) ? 1 : 0));
145 if (!(ram_sz % 2))
146 ram_sz -= 1;
147 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
148 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
149 ram_sz = 0;
150 }
151 i++;
152 }
153
154 in_win = &pex->bridge.pex_inbound_win[i];
155 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
156 out_le32(&in_win->barh, 0);
157 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
158 out_le32(&in_win->ar, PEX_IWAR_EN |
159 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
160
161 /* Enable the host virtual INTX interrupts */
162 out_le32(&pex->bridge.pex_int_axi_misc_enb,
163 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
164
165 /* Hose configure header is memory-mapped */
166 hose_cfg_base = (void *)pex;
167
168 /* Configure the PCIE controller core clock ratio */
169 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
170 ((get_pcie_clk(bus) / 1000000) * 16) / 333);
171 udelay(1000000);
172
173 /* Do Type 1 bridge configuration */
174 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
175 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
176 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
177
178 /*
179 * Write to Command register
180 */
181 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
182 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
183 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
184 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
185
186 /*
187 * Clear non-reserved bits in status register.
188 */
189 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
190 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
191 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
192
193 printf("PCIE%d: ", bus);
194
195 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
196 #define PCI_LTSSM_L0 0x16 /* L0 state */
197 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
198 if (reg16 >= PCI_LTSSM_L0)
199 printf("link\n");
200 else
201 printf("No link\n");
202 }
203
204 /*
205 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
206 * must have been set to cover all of the requested regions.
207 */
mpc83xx_pcie_init(int num_buses,struct pci_region ** reg)208 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
209 {
210 int i;
211
212 /*
213 * Release PCI RST Output signal.
214 * Power on to RST high must be at least 100 ms as per PCI spec.
215 * On warm boots only 1 ms is required, but we play it safe.
216 */
217 udelay(100000);
218
219 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
220 printf("Second PCIE host contoller not configured!\n");
221 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
222 }
223
224 for (i = 0; i < num_buses; i++)
225 mpc83xx_pcie_init_bus(i, reg[i]);
226 }
227